Press Releases

Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.

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• Oct 17, 2006

  Synopsys Enhances Saber Simulator Integration With UGS Software Through Global UGS Partner Program

  Expanded Collaboration Will Extend Saber Product Line Integration with UGS' NX MCAD and Teamcenter PLM Technology
• Oct 16, 2006

  Synopsys Unveils New Breed of DFM Products to Solve Process-Related Variation Issues at 45nm and Beyond

  Innovative Process-Aware DFM Product Family Enables Designers to Reduce Process Variability Impact and Improve Design for Advanced Semiconductor Manufacturing
• Oct 11, 2006

  Exar Selects JupiterXT Power Network Synthesis to Achieve Optimized Power Layout

  Automated Power Network Prototyping Delivers Optimized Area and Layer Trade-offs
• Oct 9, 2006

  San Jose State University Receives Charles Babbage Grant From Synopsys and Intel

  University to Receive World-Class Laboratory to Advance Education in Microelectronics Design
• Oct 9, 2006

  Synopsys Introduces 'MinChip' Technology Delivering Smallest Possible Chip Size for Volume Applications

  Synopsys JupiterXT and IC Compiler Tools Enable Die Size Optimization
• Oct 4, 2006

  Synopsys and ARM Announce Immediate Availability of CCS Noise Models for ARM Physical IP

  Next-Generation Signal Integrity Sign-off Models to Deliver Improved Accuracy and Reduced Turnaround Time
• Oct 3, 2006

  Enterasys Adopts Synopsys' VCS Native Testbench for Accelerated Verification Productivity

  SystemVerilog and the VMM Methodology Provide a Robust, Scalable Verification Environment
• Oct 2, 2006

  Displaytech Switches to Synopsys Design Compiler Tool for Next-Generation FLCOS Microdisplays

  Predictable Performance and Excellent Support Essential for Development of High-Performance Microdisplays
• Oct 2, 2006

  EDA Consortium Reports 15% Revenue Growth in Second Quarter 2006
• Sep 28, 2006

  Synopsys Recognizes Engineers' Technical Excellence With Best Paper Awards at SNUG Boston Conference

  More Than 400 Engineers Gather at Eighth Annual Regional User's Conference
• Sep 27, 2006

  Synopsys Triples Automatic Test Pattern Generation Performance for TetraMAX Test Tool

  Second Consecutive Runtime Improvement for TetraMAX Tool Offers Designers Substantial Productivity Benefits
• Sep 25, 2006

  Synopsys and First Silicon Solutions Speed Development of Large PCI Express Designs

  High-Performance Sitka Evaluation and Development Platform Allows Designers to Test and Debug Applications Using the DesignWare PCI Express IP in Hardware
• Sep 21, 2006

  Media Advisory/Alert: Synopsys at Intel Developer Forum
• Sep 20, 2006

  Virage Logic Adopts Synopsys' HSPICE Simulator as Golden Simulator for 65-nm Library Sign-off
• Sep 20, 2006

  Nikon and Synopsys Collaborate to Deliver Advanced DFM Lithography Solutions for 45nm and Below

  Solutions Target Improved Lithography Modeling Accuracy, Reduced Time-to-Silicon, and Improved Manufacturing Yield
• Sep 19, 2006

  Synopsys Donates Technology for Low Power Design to Accellera Standards Organization

  Technology Proven to Help Customers Achieve Ultra Low Power IC Designs
• Sep 19, 2006

  Samsung Extends Use of Synopsys' Alt-PSM Technology for Advanced SRAM ICs

  PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
• Sep 15, 2006

  Magma Dismisses Patent Claims Against Synopsys

  Synopsys Dedicates Scan Chain Inventions to Public Domain
• Sep 13, 2006

  Synopsys Releases Verification IP for the OCP Interface

  Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups
• Sep 8, 2006

  Synopsys Appoints Joe Logan as Senior Vice President of Worldwide Sales
• Sep 6, 2006

  Robert Dutton Chosen to Receive EDA Industry's Prestigious Kaufman Award
• Sep 5, 2006

  Synopsys Releases Mixed-Signal PHY IP for SMIC 130-nm Process

  High-Performance DesignWare IP for USB, PCIe, SATA and XAUI Now Available
• Aug 28, 2006

  Synopsys IC Compiler Enables Toshiba's Tape Out of High-Performance 90-nm Consumer Wireless Chip

  Concurrent Multi-Mode Optimization Speeds Timing Closure
• Aug 21, 2006

  Progate Adopts Design Compiler Topographical Technology for Faster Time-to-Results

  Topographical Technology Improves Designer Efficiency and Reduces Turnaround Time
• Aug 16, 2006

  Synopsys Posts Financial Results for Third Quarter of Fiscal 2006
• Aug 16, 2006

  Synopsys Broadens DFM and TCAD Portfolio With Acquisition of SIGMA-C Software AG

  Acquisition Will Enable Tighter Integration With DFM and Manufacturing Tools to Optimize Yield and Increase Predictability
• Aug 2, 2006

  ADVISORY: Synopsys Announces Earnings Release Date and Conference Call Information for the Third Quarter Fiscal Year 2006
• Aug 2, 2006

  Synopsys Extends Liberty Modeling Standard to Enable Variation-Aware Design

  Variation-based Models Built on Proven Composite Current Source Technology to Deliver Improved Accuracy
• Jul 27, 2006

  New SystemVerilog Book Helps Engineers Master the Adoption of the VMM Methodology

  VhdlCohen Publishes A Pragmatic Approach to VMM Adoption: 'A SystemVerilog Framework for Testbenches'
• Jul 26, 2006

  Electronic Tools Company Receives Synopsys Sixth Annual Tenzing Norgay Interoperability Achievement Award

  EDA Company Honored for Key Contributions to Open Source Parser for Liberty™ Library Format
• Jul 26, 2006

  Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

  Checkers Proven to Accelerate Customer Adoption of SystemVerilog Assertions to Benefit Entire Industry
• Jul 25, 2006

  Synopsys' PrimeYield Delivers Fast Turn-Around Time on Intel® Dual-Core Xeon® 5160 Processor

  Scalable DFM Checks Accelerate Time-to-Yield for Designers
• Jul 24, 2006

  Synopsys PrimeYield LCC Links to IC Compiler for Automated Correction of Lithography Problems

  Toshiba to Deploy Integrated, Production-Proven DFM Technology into Standard Layout Flow
• Jul 24, 2006

  Synopsys Extends PrimeTime and Star-Rcxt With Statistical Capabilities To Address Variation-Aware Design Challenges

  Built on Gold Standards, PrimeTime VX and Star-RCXT VX Tools Deliver Foundation for Comprehensive Variation-aware Design Solution for Sub-65nm Design
• Jul 24, 2006

  Synopsys Extends DFM Leadership With Launch of PrimeYield Tool Suite for Yield Analysis

  Integration of Production-Proven Design and Manufacturing Technology Accelerates Time to Yield
• Jul 20, 2006

  Synopsys DFT MAX Cuts Test Costs on Nanometer Designs

  More Than 50 Tapeouts Prove DFT MAX Reduces Test Time and Cost
• Jul 19, 2006

  Synopsys Galaxy Platform Reduces Power Consumption of Industry-Leading Multi- Voltage Designs

  Multiple Multi-Voltage Tapeouts Completed With Galaxy Advanced Low-Power Solution
• Jul 19, 2006

  Synopsys Delivers First 65-nm Reference Flow for IBM, Samsung and Chartered

  Common Platform Technology Reference Flow Adds Critical Area Design-for-Manufacturing Capability in IC Compiler
• Jul 18, 2006

  TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler

  Reference Flow 7.0 Incorporates Latest Technologies for Low Power and Yield Optimization to Address 65-nanometer Design Challenges
• Jul 18, 2006

  Industry Momentum Builds for the ARM-Synopsys VMM for SystemVerilog

  Users Embrace the VMM Methodology for SystemVerilog and Synopsys' VCS® Native Testbench
• Jul 13, 2006

  Semiconductor and IP Industry Leaders Join Synopsys and Si2 to Advance Liberty Modeling Standard

  Founding Technical Advisory Board Members to Hold Inaugural Meeting at Design Automation Conference in San Francisco
• Jul 12, 2006

  Synopsys 2006.06 Release of DesignWare Library Reduces Area and Delay in IC Designs

  Synopsys Expands DesignWare Library With More Than 20 New IP Components
• Jul 11, 2006

  IBM and Chartered Team With Synopsys for Mixed-Signal Connectivity IP at 65 nm

  Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes
• Jul 5, 2006

  Ross Video Selects Synopsys' VCS SystemVerilog Native Testbench to Increase Verification Productivity and Predictability

  VCS Native Testbench (NTB) and the Verification Methodology Manual (VMM) for SystemVerilog Help Accelerate Aggressive Verification Schedule
• Jun 29, 2006

  Synopsys' IC Compiler Completes Tapeout of High-Density Sunplus Consumer Design

  Sunplus Selects Synopsys Professional Services to Achieve Aggressive Schedule and Cost Goals
• Jun 28, 2006

  Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC's Nexsys(SM) 90-LP Process

  Silicon-Proven DesignWare PHY Cuts Power and Size in Half for Portable, High-Volume Consumer SoCs
• Jun 28, 2006

  Synopsys Unveils NanoTime Next-Generation Transistor-Level Static Timing Analysis Solution

  NanoTime Extends Synopsys' Leadership in Transistor-Level Simulation and Analysis
• Jun 27, 2006

  Micronas Tapes out HDTV Chip With Synopsys' IC Compiler

  IC Compiler Reduces Chip Cost by Achieving Over 90% Area Utilization
• Jun 26, 2006

  Synopsys Continues IC Compiler Momentum With 2006.06 Release

  Release Brings New Advances in Yield, Low Power, and Testability
• Jun 14, 2006

  Synopsys Chief Financial Officer Brian Beattie to Speak at the NASDAQ 17th Investor Program

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