MUNICH, GERMANY – October 27, 2008 - Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the Best Paper Awards for its 17th annual Synopsys Users’ Group (SNUG®) Europe conference, which was held October 7-8 in Munich, Germany. At the Munich event, the First Place award for Best Paper went to Jörg Christoffers of EADS Innovation Works for “Automating Saber with TCL/TK and AIM: Electrical Load Extrapolation and Schematic Generation.” Second place went to Jonathan Bromley of Doulos for “Seamless Refinement from Transaction Level to RTL Using SystemVerilog Interfaces.” Third place went to Horst Fischer, Guoxing Zhang and Holger Günther of Qimonda AG for “Evaluation of Four Popular Fastmos Tools for Simulating DRAM Circuits.” The award for Best First-Time Presenter went to Christopher J. Welham, Gunar Lorenz and Stephane Rouvillois of Coventor Sarl; Michael Kraft of the University of Southampton’s School of Electronics and Computer Science; and David King, David Combes and Mark McNie of QinetiQ for “Modeling and Simulation of Multi Degree-of-Freedom Micro-Machined Accelerometer with Sigma-Delta Modulator.” These winners were selected by the attendees.
The Technical Committee Award went to Cyrille Thomas of Bull for “Design for Test Insertion on a Very Complex VLSI Using Synopsys Galaxy Flow.” Two Technical Committee Honorable Mentions went to Frederic Hiebel of Texas Instruments Inc. for “Transition Fault Test Pattern Generation Optimization using On-Chip PLL and Implication on Compression Techniques,” and Manu Baby and Vijay Sarathi of Dubai Circuit Design for “Advanced DFT Implementation Using Synopsys DesignWare Components and Galaxy Test.” The Technical Committee awards are selected by the SNUG Technical Committee and are based on the paper’s innovation, the challenges it addresses and the overall benefit to the user community.
SNUG Europe is part of a global program that last year drew more than 6,000 integrated circuit (IC) and system design engineers to eight such technical conferences worldwide. The flagship event in San Jose, California drew record attendance of more than 2,000 Synopsys users in April 2008. Attendees represent the world’s largest semiconductor design and manufacturing companies as well as many innovative start-ups.
“We had engineers from 20 countries at SNUG Europe, which proves SNUG’s technical relevance for European semiconductor design and manufacturing,” said Frank Poppen, research engineer at OFFIS Institute for Information Technology and SNUG Europe technical chair. “For new ideas, innovations and progress, it is very stimulating to leave your office once in a while and exchange experiences with as many colleagues from as many different cultural backgrounds as possible. SNUG Europe is the perfect place for this type of interaction.”
Dr. Chi-Foon Chan, president and chief operating officer at Synopsys, addressed attendees at the technical conference with a keynote that reviewed advances in electronic products, chip design and technology requirements during the past 10 years. He also discussed current designer issues such as power, performance and productivity, and how they must be addressed by considering the physics from below and the system level issues from above.
“SNUG has always been about sharing information: designers learning from other designers and Synopsys learning from the experiences and honest feedback of our users,” said Dr. Chan. “The active participation of our users, who openly discuss their latest technical challenges, experiences and solutions, is a key reason why SNUG conferences are known as premier technical events in the EDA industry. We congratulate the best paper winners for exemplifying this information exchange and for their role in SNUG’s continued success.”
SNUG Europe Sponsors include Global Sponsors ARM, TSMC and Common Platform, as well as Gold Sponsors HP, Sun and Virage Logic. The two-day SNUG Europe conference featured a technical program with more than 60 presentations that focused on all areas of design including system-level, synthesis, verification, analog-mixed signal, low-power design, physical design, test, signoff and FPGAs. These presentations focused on the challenges that engineers face as they design complex systems for a wide array of applications. Unique to SNUG Europe is the multi-technology systems track, geared towards users in the automotive, aerospace and IC industries. For the second time, the program also included a management track designed for vice presidents and directors of engineering with program management responsibilities who must regularly consider both business and technology issues. Conference proceedings are available on the SNUG website: http://snug-universal.org/
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
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Synopsys, DesignWare, Galaxy and SNUG are registered trademarks or trademarks of Synopsys, Inc. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contact:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
sgulizia@synopsys.com
Jo Harrington
EML
44161 973 9352
joanneh@eml.com
SOURCE: Synopsys, Inc.
CONTACT: editorial, Sheryl Gulizia, +1-650-584-8635,
sgulizia@synopsys.com, or, Jo Harrington, +44161 973 9352
Web site: http://www.synopsys.com/
