Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Jul 13, 2016DesignWare IP Reduces USB Silicon Area by Up to 50 Percent with Near 0 W Standby Power Consumption for Longer Battery Life
- Jul 12, 2016New ATPG Engines Reduce Test Cost, Pattern Count by 25 Percent with Order of Magnitude Faster Runtime
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Jul 12, 2016Independent Functional Safety Evaluation Provides Highest Level of Safety-Related Tool Confidence
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Jul 12, 2016New ATPG Engines Substantially Reduce Test Pattern Count for Lower Test Cost
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Jul 12, 2016New ATPG Solution Reduces Pattern Count by up to 50% and Significantly Shortens ATPG Runtime
- Jul 11, 2016Strengthens Software Integrity Offering for Web and Mobile Applications, Automotive Systems and Chinese Market
- Jul 11, 2016Synopsys' Process Explorer and Raphael accurately simulate parasitic resistance of alternative metals and liner-barrier materials at the 7nm node and beyond
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Jul 6, 2016Adaptor Connects HAPS® Prototyping System with Juno ARM® Versatile™ Express Board to Speed SoC Prototyping and Integration for ARMv8-A based Designs
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Jun 27, 2016Synopsys Synplify Pro Software Delivers Superior Logic Synthesis Results for Users of Lattice Semiconductor Programmable Logic Devices
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Jun 21, 2016New Enhanced PCI Express IP Supports 16 GT/s and Latest Specification, Targeting High-Performance Applications
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Jun 16, 2016Latest Release Delivers New Capabilities for the Design of Manufacturable Photonic Integrated Circuits
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Jun 8, 2016Collaboration Delivers Best-In-Class Power, Performance and Area with IC Compiler II
- Jun 8, 2016DesignWare DDR4 IP Solution Enables Servers to Solve Complex Computation Problems Faster
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Jun 6, 2016Comprehensive Synopsys Solution Enables Accelerated Verification of Next-Generation SoCs including Automotive, Secure Connectivity and Smart Connected Products
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Jun 6, 20164X emulation performance enables fast software schedules for next-generation SoCs
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Jun 1, 2016DesignWare EV6x Family Integrates Scalar, Vector Processors and a Convolution Neural Network Engine for High Accuracy Vision Processing
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May 31, 2016RTL Congestion Analysis and Tight Correlation to Place-and-Route Shorten Design Schedules and Improve Predictability
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May 29, 2016Optimized Reference Implementation Using Galaxy Design Platform Available for New ARM Cortex-A73 Processor
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May 26, 2016
- May 25, 2016Generic Timer Module, CAN and FlexRay Models for Synopsys Virtualizer Development Kits Enable Early Software Development and Improve Software Quality
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May 24, 2016Subsystem Verification Solution Features Integrated Testbench Generation, Subsystem Level Test Suite, System Monitor, Coverage Checks, Performance Tests and Analysis
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May 23, 2016Enables Earlier Co-Optimization of Devices, Processes, Materials and Design
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May 19, 2016Samsung and Synopsys Collaborate to Deliver Custom Compiler-ready iPDK
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May 18, 2016Q2 2016 Financial Highlights
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May 17, 2016
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May 17, 2016Best-In-Class Power, Performance and Area Lead to Selection of IC Compiler II
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May 17, 2016Superior QoR Leads HiSilicon, Movidius to Select IC Compiler II
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May 11, 2016ASIL D Ready Certified ARC EM Processors with Safety Enhancement Package Accelerate ISO 26262 Certification Time by up to Six Months
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May 10, 2016Certification Provides Highest Degree of Safety-Related Confidence and Accelerates Functional Safety Qualification
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May 2, 2016Native SystemVerilog VIP Enables Ease of Development for HMC Solutions
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May 2, 2016New iPDKs Streamline Development of Analog/Power and Mixed-signal Designs for High-growth Markets
- Apr 26, 2016DesignWare IP Compliant with the Latest MIPI I3C Specification Delivers High Bandwidth and Scalability
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Apr 13, 2016Native SystemVerilog VIP Features Built-in Coverage, Verification Planning, Protocol-Aware Debug and Source Code Test Suites
- Apr 5, 2016Synopsys' Software Security Testing Tools Used in UL's New Certification Program for Network-connectable Devices
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Apr 5, 2016Native SystemVerilog VIP and Source Code Test Suites for CAN 2.0/FD/TT, LIN, FlexRay and Ethernet AVB
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Mar 31, 2016Certification Includes Industry-leading IC Compiler II Place and Route Solution
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Mar 30, 2016Shortens FinFET Custom Design Tasks from Days to Hours
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Mar 30, 2016TSMC and Synopsys collaborate to provide Custom Compiler-ready iPDKs
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Mar 30, 2016Template Assistants Shorten Layout Tasks
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Mar 30, 2016In-Design Assistants Reduce Design Iterations
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Mar 30, 2016Innovative Assistants Provide Productivity Boost
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Mar 29, 2016Breakthrough Lint-Turbo Technology Delivers 10X Performance, 5X Improvement in Memory, and 3X Faster Design Closure
- Mar 27, 2016Comprehensive Suite of Software Security Testing Solutions Helps Reduce Risk, Cost and Time to Market
- Mar 24, 2016Cheetah Fine-Grained Parallelism Technology Enables up to 5X RTL and 30X Gate-level Simulation Acceleration
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Mar 23, 2016Major Enhancements Enable Designers to Work Smarter for Faster Closure on FinFET Designs
- Mar 14, 2016DesignWare Logic Library, Embedded Memory, Interface, and Analog IP on TSMC 16FFC Cuts Power Consumption for Advanced SoCs
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Mar 14, 2016Certification Includes Digital, Signoff and Custom Implementation Tools from Synopsys Galaxy Design Platform
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Mar 10, 2016Latest Release Enables Advanced Design of LEDs, OLEDs and Displays
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Mar 9, 2016Latest Releases Deliver Human Vision Simulation Updates, User Interface Enhancements, and Expanded Libraries for Automotive Lighting Design and Analysis
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Mar 7, 2016Latest Version of Illumination Design Software Enables Rapid Virtual Prototyping and Optimization of General Lighting Systems
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Mar 2, 2016Acquires Leader in Fault Simulation
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Mar 2, 2016Multiple Customer Tapeouts Completed with Synopsys Flow on the 14nm Process
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Feb 25, 2016Comprehensive Suite of Software Security Testing Solutions Helps Reduce Risk, Cost and Time to Market
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Feb 24, 2016Native SystemVerilog HDMI VIP Includes Built-In Coverage, Verification Planning and Protocol-Aware Debug
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Feb 23, 2016Validated Interoperability of DesignWare Bluetooth Smart PHY IP with Mindtree's Link Layer and Software Stack IP Reduces Integration Risk
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Feb 23, 2016Extends Verdi's Market-Leading SoC Debug Platform with Comprehensive and Automated AMS Debug Capabilities
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Feb 22, 2016Complete Platform and Strong Support Enable CSMC to Deliver Sub-180-nanometer Foundry Offerings Faster
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Feb 18, 2016Integration of Intrinsic-ID PUF Solution and Synopsys ARC EM Processor with SecureShield Enables Implementation of Security Functions without Requiring Dedicated Security Processor
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Feb 18, 2016Combination of Cypherbridge uSSL SDK and DesignWare SSL/TLS/DTLS Security Protocol Accelerator Speeds Software Development
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Feb 17, 2016Q1 2016 Financial Highlights
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Feb 11, 2016Availability of 14-nm Runsets Provides Benefits of In-Design Productivity and Faster Physical Verification
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Feb 3, 2016Eliminates Need for Third-party Environment, Accelerates Analog Verification
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Feb 3, 2016USB-IF Certified IP Ensures Interoperability and Lowers Integration Risk for High-Performance, Low-Power SoC Designs
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Feb 1, 2016First Verification IP Product Line That Includes All SAS Interface Speed Configurations
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Jan 27, 2016DesignWare Smart Data Fusion IP Subsystem Integrates Latest ARC EM DSP Processors, Peripherals and Software to Boost Signal Processing Performance and Reduce Energy Consumption
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Jan 26, 2016DesignWare IP Solution Accelerates Development of SoCs Delivering Secure Video, Data and Power over a Single USB Type-C Connector
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Jan 26, 2016Smarter Resource Management Significantly Improves Customer Design Efficiency
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Jan 25, 2016Solution Enables Efficient Reuse of UPF 3.0 System-Level IP Power Models for Early Analysis of SoC Architectures for Power and Performance
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Jan 20, 2016Offers a Smarter Way to Get PrimeTime Signoff-Quality Timing Models with Available Compute Resources
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Jan 6, 2016High-Quality IP Enables Integration in Two Weeks and Speeds Time to Volume
- Jan 5, 2016Latest Version of Static Analysis Solution Adds Coverage for PHP, Python; Improves Security Analysis, Integration Support, and Ease of Use
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Dec 17, 2015High-Quality IP Combined with Synopsys' HAPS-70 FPGA-Based Prototyping System and Professional Services Accelerate Time-to-Market
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Dec 14, 2015Achieves 5 Percent Smaller Area with Accelerated Design Closure
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Dec 9, 2015CODE V Optical Design Software Release 10.8 Is Now Generally Available
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Dec 8, 2015Latest Releases Accelerate Design of Complex, State-of-the-Art Photonic Components and Systems
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Dec 2, 2015Q4 2015 Financial Highlights
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Nov 24, 2015Qualification Brings Proven, Transformational Benefits of IC Compiler II to Adopters of Samsung Foundry's Latest FinFET Process
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Nov 23, 2015Native SystemVerilog Ethernet VIP Features Built-in Coverage, Verification Planning, Protocol-Aware Debug and Source Code Test Suites
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Nov 17, 2015Synopsys Has Identified and Closed Method Used to Gain Access; Investigation Determines No Customer Project or Design Data in the Portal Was Accessed
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Nov 10, 2015Collaboration Provides Synopsys with Access to the Latest ARM® Fast Models for Use with Virtualizer Development Kits
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Nov 10, 2015Expands Comprehensive VIP library for ARM® AMBA® protocols with System-Level Test Suites, System Monitor, Protocol-aware Debug and Performance Analysis; Adds VIP for New AMBA 5 AHB5 Standard
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Nov 9, 2015Reference Flow Using Galaxy Design Platform Available for Early Customer Engagement
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