MOUNTAIN VIEW, Calif., May 24, 2017 /PRNewswire/ --

Highlights:

• Samsung's certification of Synopsys Custom Platform for 28FDS includes HSPICE circuit simulation, Custom Compiler layout implementation, StarRC parasitic extraction and IC Validator physical signoff
• Custom Compiler placement and routing assistants cut 28FDS layout effort by up to 30%
• Silicon-correlated HSPICE models include self-heating effects and improve simulation accuracy for Samsung 28FDS process technology

Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys' custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE^® golden-accuracy circuit simulation, Custom Compiler^™ visually-assisted layout automation, StarRC^™ gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT and Connectivity.

Custom Compiler's user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS process design kit (PDK) in the industry-standard interoperable process design kit (iPDK) format.

"Samsung Foundry's 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. "We worked with Synopsys to certify Synopsys' custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development."

Synopsys' custom design platform offers advanced features to improve reliability and manage variability for automotive and IoT designs. Comprehensive aging simulation and Monte Carlo analysis is driven by a common simulation environment, making it easier to analyze reliability. Advanced reporting, cross-probing and visualization features enable automotive designers to identify and solve reliability problems faster. Accurate net-based parasitic extraction with the StarRC tool during layout helps control design variability with little iteration. The Custom Compiler In-Design assistant with IC Validator catches DRC violations during layout and reduces physical signoff iterations. The platform also enables the use of simulation results to directly check electromigration effects during layout.

"Samsung Foundry's certification of Synopsys' custom design platform is important to our mutual customers developing complex designs," said Bijan Kiani, vice president of product marketing at Synopsys. "Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity."

About Custom Compiler

Custom Compiler provides an open environment spanning schematics, simulation analysis and layout. Unified with Synopsys' circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution. Custom Compiler shortens the time it takes to complete FinFET design tasks from days to hours. Its visually-assisted automation leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler's visually-assisted automation provides four types of assistants: Layout, In-Design, Template and Co-Design. Layout Assistants speed layout with user-guided automation of placement and routing. In-Design Assistants reduce design iterations by catching physical and electrical errors before signoff verification. Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Co-Design Assistants combine IC Compiler^™ II place-and-route with Custom Compiler into a unified solution for custom and digital implementation. Custom Compiler is based on the industry-standard OpenAccess database. For more information about Custom Compiler, visit https://www.synopsys.com/implementation-and-signoff/custom-implementation/custom-compiler.html .

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
Carole Murchison
Synopsys, Inc.
650-584-4632
carolem@synopsys.com

SOURCE Synopsys, Inc.