MOUNTAIN VIEW, Calif., Sept. 11, 2017 /PRNewswire/ --
Highlights:
Synopsys, Inc. (Nasdaq: SNPS) today announced the successful tape-out of a broad portfolio of DesignWare® Foundation and Interface PHY IP for TSMC's 7-nm process technology, including logic libraries, embedded memories, embedded test and repair, USB 3.1/2.0, USB-C 3.1/DisplayPort 1.4, DDR4/3, MIPI D-PHY, PCI Express® 4.0/3.1, Ethernet and SATA 6G. Additional DesignWare IP, including LPDDR4x, HBM2 and MIPI M-PHY, is scheduled to tape out in 2017. TSMC's 7-nm process enables designers to achieve up to a 60 percent power reduction or 35 percent performance increase compared to the 16FF+ process. By providing a portfolio of IP on TSMC's latest 7-nm process technology, Synopsys enables designers to meet the power and performance requirements of their mobile, automotive and high-performance computing applications.
"For more than a decade, Synopsys and TSMC have collaborated closely to provide high-quality IP for many generations of TSMC's processes," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Synopsys' tape-out of a broad portfolio of DesignWare Foundation and Interface IP for TSMC's 7-nm process demonstrates its ongoing leadership in providing IP that enables our mutual customers to take advantage of the power, performance and area improvements offered by the process, while accelerating designers' time to volume production."
"As the leading provider of physical IP with more than 100 FinFET tape-outs, Synopsys makes significant investments in developing IP for the most advanced processes so that our customers can implement the necessary functionality to differentiate their SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "The successful tape-out of a broad range of DesignWare Foundation and Interface IP on TSMC's 7-nm technology gives designers confidence that they can integrate our IP into their SoC with significantly less risk and accelerate their project schedule."
Availability
A portfolio of DesignWare Foundation and Interface IP for the TSMC 7-nm process is available now. The STAR Memory System™ solution is also available now for all TSMC process technologies.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
Forward-Looking Statements
This press release contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected release and benefits of LPDDR4x, HBM2 and MIPI M-PHY DesignWare IP. Any statements that are not statements of historical fact may be deemed to be forward-looking statements. These statements involve known and unknown risks, uncertainties and other factors that could cause actual results, time frames or achievements to differ materially from those expressed or implied in the forward-looking statements. Other risks and uncertainties that may apply are set forth in the "Risk Factors" section of Synopsys' most recently filed Quarterly Report on Form 10-Q. Synopsys undertakes no obligation to update publicly any forward-looking statements, or to update the reasons actual results could differ materially from those anticipated in these forward-looking statements, even if new information becomes available in the future.
Editorial Contact:
Monica Marmie
Synopsys, Inc.
650-584-2890
monical@synopsys.com
SOURCE Synopsys, Inc.
