Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Jun 14, 2005ARM, TSMC, Virage Logic and Library Technologies Gear Up to Support CCS-enabled 90nm Libraries
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Jun 10, 2005Scalable Distributed Processing Reduces Physical Verification Processing Time from Days to Hours
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Jun 9, 2005Synopsys' Galaxy Design Platform Provides Advanced Power Closure and Enhanced Yield Capabilities for Reference Flow 6.0
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Jun 8, 2005Synopsys to Deliver Complete System to Implementation Solution for Power Architecture Designs
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Jun 7, 2005IC Compiler Delivers 10 Percent Higher Speed With Faster Time-To-Results
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Jun 7, 2005Synopsys' PSM, Hercules PVS, Proteus OPC and TCAD Offer FastDFM Flow Turnaround Time
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Jun 6, 2005DesignWare Digital Controller Cores and PHY IP Available Today for the PCI Express 1.1 Standard
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Jun 6, 2005Proven SATA Verification IP Lowers Risk and Speeds Verification for SoC Designers
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May 31, 2005Latest Version of the VCS® Solution Speeds Standards-Based Verification by Unifying SystemVerilog and SystemC™ Languages in a Single Tool
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May 31, 2005VCS® Native Testbench Technology and Comprehensive Coverage Enable Huawei to Achieve First-Silicon Success in Less Time
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May 25, 2005Synopsys DesignWare® PHY IP Enables Reliable USB Connectivity for IBM and Chartered Foundry Customers
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May 25, 2005Complete RTL to Production-Ready GDSII Flow Speeds 90-nm Designs
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May 24, 2005i-Virtual Stepper System Integrates Lithography Simulation and Automation to Deliver Improved Mask Turn-Around Time and Yield
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May 23, 2005Design Compiler® 2005 Delivers Accurate Correlation to Post-Layout Timing for RTL Designers
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May 18, 2005
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May 12, 2005Certified Digital and PHY IP Gives Designers the Flexibility to Choose From 130nm or 90nm Processes
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May 10, 2005Leading Digital Core Combined With High-performance PHY Lowers Risk for SoC Designers
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May 10, 2005Advanced Coverage and Testbench Technologies in the Synopsys Discovery™ Verification Platform Enable Robust Validation of Faraday's Processor IP
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May 9, 2005Extending Sign-off in the Galaxy™ Design Platform to Voltage-Drop and EM Analysis
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Apr 26, 2005Full Portfolio of Synopsys' IP Expands GUC's Deep Submicron Offering
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Apr 20, 2005Vera Tool Offers the Thorough Verification Necessary for Mission-Critical Network Protection
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Apr 20, 2005VCS Native Testbench Helps CreVinn Speed Testbench Development and Performance to Deliver a Higher Level of Verification
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Apr 4, 2005VCS Native Testbench Technology Helps Atmel Find Critical Bugs in Less Time
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Mar 30, 2005Synopsys Expands University Program by Donating Technology Licenses to Southern Methodist UniversitySMU to Use Synopsys Tools for Industrial Research in Embedded System Design
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Mar 14, 2005Leading-edge Customers Attest to Achieving Increased Performance and Productivity
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Mar 8, 2005Benefits Include Support for SPIRIT 1.0 Standard and Integration With Galaxy™ and Discovery™ Platforms
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Mar 7, 2005DFT Compiler Max Delivers 10-50x Test Time Reduction in the Smallest Area With the Ease of 1-Pass Scan Synthesis
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Mar 1, 2005Synopsys' Distributed Processing and Scalable Architecture Improve Time to Yield While Maintaining Accuracy
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Feb 28, 2005ESP Boosts Verification Productivity by 2X for Memory Compilers
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Feb 28, 2005Galaxy™ Reference Flow Enables Faster Integration of ARM IEM Technology-Enabled IP for Low Power
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Feb 23, 2005Reduces Development Time of LCD TV Driver SoC by Half
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Feb 14, 2005VCS Native Testbench Migration Service Provides Access to Up to 5X Faster Verification Performance
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Feb 14, 2005Powerful Testbench Automation in Synopsys Discovery™ Verification Platform Enables NetSilicon to Achieve First-Silicon Success
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Feb 14, 2005Latest Release of VCS® Solution Extends Verification Performance and Effectiveness With New, Powerful Native Testbench Capabilities
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Feb 14, 2005Industry Leaders to Demonstrate Immediate Benefits of Using SystemVerilog for Advanced Verification
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Feb 9, 2005Advanced Hybrid Formal Verification Technology Awarded Top Honor in Design Verification Category
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