Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Oct 10, 2005Communications Leader Uses Synopsys' Tools and Flows From Design Through Physical Implementation
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Oct 4, 2005ARM and Synopsys Collaborate to Demonstrate Galaxy Design and Discovery Verification Flow for ARM Cortex-A8 Processor Implementation
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Oct 4, 2005Comprehensive Design Kit for X-FAB's 0.6-Micron Process Improves Quality and Speeds Time to Market
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Oct 4, 2005Accurate OPC Modeling Critical for Accelerating Time to Yield
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Oct 3, 2005New, Accurate Model Speeds Time to Results by 2X
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Oct 3, 2005Acquisition Will Establish EDA Industry's First Direct Connection into Fabrication Processes
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Oct 3, 2005Enhanced Reference Methodology delivers 10 percent higher performance
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Oct 3, 2005Synopsys and Dassault Partner to Provide Improved Electro-Mechanical Design
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Sep 26, 2005Mixed -Signal IP Complements Synopsys' Market-Leading Portfolio of Serial Interface Controllers
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Sep 26, 2005Verification IP Product Combines with Advanced Methodologies and Tools to Deliver a High-Performance Integrated Verification Environment
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Sep 26, 2005Testing Conducted With Synopsys' Wireless USB Device Controller IP and Alereon's WiMedia Ultra-Wideband PHY
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Sep 26, 2005Companies Lead Industry With Hardware and Software Interoperability Testing
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Sep 26, 2005Early IP Availability From Synopsys Drives Wireless USB Integration Into Next Generation SoCs
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Sep 26, 2005Pioneer-NTB Delivers Standards-Based, Mixed-HDL Verification Built on Synopsys' Proven VCS® Technology
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Sep 21, 2005Automated Macro Placement and Power Network Synthesis Reduces Design Planning Time Up to 10x
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Sep 21, 2005Verification Effort Reduced With Certified DesignWare Verification IP
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Sep 21, 2005New ARM-Synopsys Book Provides Blueprint for System-on-Chip Verification Success Using SystemVerilog
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Sep 21, 2005Addition Enables Easy Adoption of AMBA 3 AXI Protocol with Automated Subsystem Assembly and Comprehensive Set of Synthesizable and Verification IP
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Sep 21, 2005VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog
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Sep 19, 2005Leading-Edge Companies Achieve Significant Productivity Gains and Cost Savings Using New Flip Chip Methodology
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Sep 14, 2005Syracuse to Receive Sun Workstations and Synopsys EDA Software and Licenses
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Sep 14, 2005Dismissal Resolves Litigation With No Additional Expense to Synopsys
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Aug 23, 2005Demo at Intel Developer Forum Shows Two-Way Transfer of Large Multimedia Files using the USB-IF's Wireless USB and WiMedia UWB Platform
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Jul 27, 2005ASIC and System Developer Adopts Synopsys' Discovery™ Verification Platform for 90-Nanometer Chip
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Jul 19, 2005Latest Flow for 0.13-micron Process Offers Advanced Floor Planning, Signal Integrity and Reliability Features
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Jul 12, 2005New Specification Targets Increasing File Size, Need for Common Data Format
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Jun 27, 2005Design for Yield Capabilities Enable Renesas Technology to Achieve Yield Goals in Wireless SoC
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Jun 22, 2005Comprehensive Built-in Coverage Metrics in Synopsys' VCS® Solution Increase Verification Quality for STMicroelectronics' 90 Nanometer HDTV Processor Chip
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Jun 21, 2005Semiconductor Industry Executives Reflect on 40th Anniversary of Moore's Law
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Jun 15, 2005Collaboration on Interoperable Design Solutions to Benefit User Community
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Jun 14, 2005
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Jun 14, 2005Galaxy Platform Enables 50 Percent Power Savings in SoC Design
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Jun 14, 2005ARM, TSMC, Virage Logic and Library Technologies Gear Up to Support CCS-enabled 90nm Libraries
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Jun 10, 2005Scalable Distributed Processing Reduces Physical Verification Processing Time from Days to Hours
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Jun 9, 2005Synopsys' Galaxy Design Platform Provides Advanced Power Closure and Enhanced Yield Capabilities for Reference Flow 6.0
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Jun 8, 2005Synopsys to Deliver Complete System to Implementation Solution for Power Architecture Designs
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Jun 7, 2005IC Compiler Delivers 10 Percent Higher Speed With Faster Time-To-Results
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Jun 7, 2005Synopsys' PSM, Hercules PVS, Proteus OPC and TCAD Offer FastDFM Flow Turnaround Time
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Jun 6, 2005DesignWare Digital Controller Cores and PHY IP Available Today for the PCI Express 1.1 Standard
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Jun 6, 2005Proven SATA Verification IP Lowers Risk and Speeds Verification for SoC Designers
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May 31, 2005Latest Version of the VCS® Solution Speeds Standards-Based Verification by Unifying SystemVerilog and SystemC™ Languages in a Single Tool
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May 31, 2005VCS® Native Testbench Technology and Comprehensive Coverage Enable Huawei to Achieve First-Silicon Success in Less Time
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May 25, 2005Synopsys DesignWare® PHY IP Enables Reliable USB Connectivity for IBM and Chartered Foundry Customers
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May 25, 2005Complete RTL to Production-Ready GDSII Flow Speeds 90-nm Designs
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May 24, 2005i-Virtual Stepper System Integrates Lithography Simulation and Automation to Deliver Improved Mask Turn-Around Time and Yield
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