Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Mar 27, 2006
Enhanced STARCAD-21 RTL-to-GDSII Production Flow Ready for Deployment at Major Japanese Semiconductor Companies
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Mar 22, 2006
Galaxy Design Platform Delivering Predictable Time-to-Results Through Sign-off Correlation to Silicon
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Mar 21, 2006
Processor Implementation and Verification Enabled by Powerful Tools From Synopsys' Galaxy and Discovery Platforms
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Mar 20, 2006
More Than 150 Companies Worldwide Have Adopted Synopsys' SystemVerilog Solutions to Create Today's Hottest Electronics Products
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Mar 20, 2006
VCS Verification Library Enables Rapid Adoption of SystemVerilog With Full Support of the Verification Methodology Manual (VMM) for SystemVerilog
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Mar 15, 2006
Sign-Off Flow With Star-RCXT Delivers High Predictability
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Mar 8, 2006
DesignWare® Library Core's Portability and Accessibility Cited by IBM in Award Presentation
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Feb 27, 2006
Production-Ready Environment Integrates Proven RTL-to-GDSII Flow With New Utilities to Improve Design Productivity and Tapeout Predictability
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Feb 27, 2006
Flow Supports IC Compiler for Common Platform's Low-Power Process
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Feb 22, 2006
IEEE Working Group Chairman Awards and Certificates of Recognition Presented to Synopsys Engineers
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Feb 15, 2006
Synopsys Galaxy Design Platform Delivers Complete Flow for Ultra-Low-Power Design
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Feb 8, 2006
SystemVerilog Testbench Automation Technology Awarded Top Honor in Design Verification Category
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Feb 6, 2006
Enables Longer Battery Life and Lower Cost for Mobile and High-Volume Consumer Products
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Jan 25, 2006
Japanese-Language Edition of the Manual to Be Published by CQ Publishing
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Jan 24, 2006
Synopsys Is First to Deliver PCI Express Gen II Digital IP for Increased Bandwidth in Networking, Embedded and Computer Applications
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Jan 10, 2006
IP-Enabled Services Firm Joins Synopsys' SystemVerilog Catalyst Program
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Dec 19, 2005
AMCC Deploys SystemVerilog Verification Environment With Synopsys' VCS® Native Testbench and Reference Verification Methodology
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Dec 19, 2005
PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
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Dec 14, 2005
Provides Complete Set of Standards-Based I/O Libraries for General Purpose and High-Performance Applications
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Dec 7, 2005
DesignWare PHYs for Hi-Speed USB 2.0 and Hi-Speed USB OTG Developed with TSMC's Production-Proven 90-nm Libraries
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Dec 6, 2005
Increased Predictability of Manufacturing Process through TCAD Lowers Product Development Cost and Time
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Nov 28, 2005
IC Compiler Fits Easily in the Agere Flow, Delivers Higher Performance
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Nov 21, 2005
Reference Design Flow Features Low Power Management and Design-for-Manufacturing Automation Capabilities
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Nov 8, 2005
TetraMAX® ATPG Performance Speedup Combined with a New Waveform Debugger Streamline Test Pattern Generation for Complex Designs
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Nov 7, 2005
Composite Current Source Model First to Combine Timing, Noise and Power
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Nov 7, 2005
Designers Benefit from Enhanced Productivity and Reduced Design Margins
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Nov 2, 2005
Combined Technology Can Read, Write and Provide On-The-Fly View of Compressed Files
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Nov 1, 2005
DFT MAX Achieves 90% Test Data Volume Reduction for Flat Display TV Controller
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Oct 31, 2005
Exar Develops and Deploys Advanced SystemVerilog Verification Environment and Reference Model with VCS® Native Testbench Technology
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Oct 24, 2005
TetraMAX Diagnostics Enable TSMC to Accelerate Yield Ramp on Deep Submicron Designs
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Oct 19, 2005
Advanced Testbench Techniques Critical for Multi-Protocol Verification Environment at Chip and System Levels
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Oct 19, 2005
Project Methodology Leverages Assertions, Functional Coverage, Constrained-Random Stimulus Generation and PCI Express® Verification IP
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Oct 17, 2005
Sentaurus Sets New Standard in TCAD Simulation Capabilities for Semiconductor Process, Device, Circuit and System Analysis, and Parametric Yield Optimization
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Oct 10, 2005
Communications Leader Uses Synopsys' Tools and Flows From Design Through Physical Implementation