Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Jul 27, 2005
ASIC and System Developer Adopts Synopsys' Discovery™ Verification Platform for 90-Nanometer Chip
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Jul 19, 2005
Latest Flow for 0.13-micron Process Offers Advanced Floor Planning, Signal Integrity and Reliability Features
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Jul 12, 2005
New Specification Targets Increasing File Size, Need for Common Data Format
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Jun 27, 2005
Design for Yield Capabilities Enable Renesas Technology to Achieve Yield Goals in Wireless SoC
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Jun 22, 2005
Comprehensive Built-in Coverage Metrics in Synopsys' VCS® Solution Increase Verification Quality for STMicroelectronics' 90 Nanometer HDTV Processor Chip
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Jun 21, 2005
Semiconductor Industry Executives Reflect on 40th Anniversary of Moore's Law
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Jun 15, 2005
Collaboration on Interoperable Design Solutions to Benefit User Community
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Jun 14, 2005
Galaxy Platform Enables 50 Percent Power Savings in SoC Design
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Jun 14, 2005
ARM, TSMC, Virage Logic and Library Technologies Gear Up to Support CCS-enabled 90nm Libraries
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Jun 10, 2005
Scalable Distributed Processing Reduces Physical Verification Processing Time from Days to Hours
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Jun 9, 2005
Synopsys' Galaxy Design Platform Provides Advanced Power Closure and Enhanced Yield Capabilities for Reference Flow 6.0
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Jun 8, 2005
Synopsys to Deliver Complete System to Implementation Solution for Power Architecture Designs
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Jun 7, 2005
IC Compiler Delivers 10 Percent Higher Speed With Faster Time-To-Results
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Jun 7, 2005
Synopsys' PSM, Hercules PVS, Proteus OPC and TCAD Offer FastDFM Flow Turnaround Time
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Jun 6, 2005
DesignWare Digital Controller Cores and PHY IP Available Today for the PCI Express 1.1 Standard
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Jun 6, 2005
Proven SATA Verification IP Lowers Risk and Speeds Verification for SoC Designers
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May 31, 2005
Latest Version of the VCS® Solution Speeds Standards-Based Verification by Unifying SystemVerilog and SystemC™ Languages in a Single Tool
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May 31, 2005
VCS® Native Testbench Technology and Comprehensive Coverage Enable Huawei to Achieve First-Silicon Success in Less Time
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May 25, 2005
Synopsys DesignWare® PHY IP Enables Reliable USB Connectivity for IBM and Chartered Foundry Customers
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May 25, 2005
Complete RTL to Production-Ready GDSII Flow Speeds 90-nm Designs
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May 24, 2005
i-Virtual Stepper System Integrates Lithography Simulation and Automation to Deliver Improved Mask Turn-Around Time and Yield
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May 23, 2005
Design Compiler® 2005 Delivers Accurate Correlation to Post-Layout Timing for RTL Designers
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