Cloud native EDA tools & pre-optimized hardware platforms
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Highlights: Ultra-low power DesignWare Die-to-Die PHY IP delivers less than 1pJ/bit for optimal energy efficiency in hyperscale data centers Compact analog front-end enables reliable links up to...
Highlights: DesignWare PHY IP in development on TSMC's N5P process includes USB, DisplayPort, DDR, LPDDR, HBM, PCI Express, Ethernet, MIPI, and HDMI DesignWare Foundation IP on TSMC's N5P process...
Highlights: DesignWare IP portfolio for GLOBALFOUNDRIES 12LP FinFET process includes Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters...
Highlights: Synopsys' Fusion Design Platform enables faster implementation with optimized PPA for Arm processors QuickStart Implementation Kit (QIK) using Arm Artisan Physical IP and POP IP,...
Highlights: DesignWare VESA DSC IP is compliant with the VESA DSC 1.1 and 1.2a standards, delivering the required 120Hz refresh rate for up to 10K resolutions Configurable IP scales up to 16...