Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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May 11, 2020High-Quality DesignWare Interface and Foundation IP Deliver Leading Power, Performance and Area
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May 1, 2020Synopsys Placed in Highest and Furthest Overall Position for its Ability to Execute and Completeness of Vision Two Years in a Row
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Apr 28, 2020Unique platform delivers automation and visualization for 2.5D/3D package design and implementation, with power, thermal, and noise-aware optimization
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Apr 23, 2020Content, now available, includes video from Synopsys co-CEO Aart de Geus discussing SNUG and new product introductions
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Apr 13, 2020ZeBu's Performance Enabled First Silicon Success of Tensor Streaming Processor Architecture
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Apr 7, 2020DesignWare ARC HS6x Processors Based on New 32/64-bit ARCv3 Instruction Set Architecture Extend Addressable Memory, Scale Up To 12 Cores
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Apr 6, 2020Synopsys' Prototyping Solutions Enable Faraday Customers to Accelerate Time-to-Market with Concurrent Hardware and Software Development
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Apr 2, 2020Broad Deployment of Synopsys' Fusion Design Platform Accelerating Delivery of Market-shaping Solutions
Mar 31, 2020DesignWare PHY and Controllers Operate at Up to 24 Gb/s for High-Performance Imaging and Automotive SoCs-
Mar 30, 2020Latest Photonic Solutions Portfolio Accelerates Design of AR/VR Systems, Optical Communications, and PICs
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Mar 27, 2020Co-CEO to Provide Brief Commentary on COVID-19 Situation
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Mar 26, 2020Silicon-Proven DesignWare IP for PCI Express 5.0 and DDR4 Delivers Low Latency and High Bandwidth for Data-Intensive Workloads
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Mar 25, 2020Latest Agreement Builds on SiFive's Successful Use of Synopsys Solutions
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Mar 24, 2020Version 9.0, Now Available, Brings Improved Polarization Modeling, Expanded Stray Light Analysis, and Optimization of Curved Display Systems
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Mar 23, 2020New Native System Verilog Ethernet VIP Complements Synopsys' 112G High-Speed SerDes PHY IP to Enable High-Performance Cloud Computing Solutions
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Mar 19, 2020DesignWare 56G PHY Delivers Leading Power and Performance with High Reliability
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Mar 16, 2020Unique RTL Tuning Environment Reduces Physical Design Iterations
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Mar 11, 2020Introducing Synopsys DSO.ai™: The world's first autonomous AI application for chip design
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Mar 11, 2020New Machine Learning-Based Simpleware ScanIP Option Provides 20-50 Times Speedup and Precisely Automates Previously Manual Segmentation for Medical Device Design and Pre-Surgical Planning
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Mar 10, 2020Alphawave Adopts Synopsys Solution to Accelerate Design of High-speed Connectivity IP
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Mar 4, 2020Recent Advances in Machine Learning (ML) Technologies Extend Synopsys' QoR Leadership
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Feb 27, 2020Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise
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