Cloud native EDA tools & pre-optimized hardware platforms
All News Releases
Su | Mo | Tu | We | Th | Fr | Sa |
---|---|---|---|---|---|---|
Su | Mo | Tu | We | Th | Fr | Sa |
---|---|---|---|---|---|---|
Highlights: Himax WiseEye ASIC platform is optimized for application developers deploying machine learning on battery-powered AIoT devices Synopsys DesignWare ARC Data Fusion IP Subsystem with...
Highlights: Synopsys TestMAX XLBIST solution delivers higher fault coverage and shorter test time by overcoming silicon issues that impede traditional self-test solutions Synopsys TestMAX XLBIST...
Highlights Acquisition of eSilicon IP will expand Synopsys' existing DesignWare Embedded Memory and Interface IP portfolio Acquisition will enable Synopsys to further scale its IP offering to...
Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung, a global leader in enterprise mobility and information technology, has adopted the Synopsys VC LP™ solution, part of the Verification...
Highlights: AMD standardizes on ZeBu Server 4, expanding emulation capacity to accelerate time-to-market for processor, graphics, and gaming chips ZeBu supports the AMD development strategy to...
Highlights: Ultra-low power DesignWare Die-to-Die PHY IP delivers less than 1pJ/bit for optimal energy efficiency in hyperscale data centers Compact analog front-end enables reliable links up to...
Synopsys, Inc. (Nasdaq: SNPS) today announced that it has shipped more than 3,000 HAPS®-80 prototyping systems since its introduction. HAPS-80 is deployed at more than 100 companies worldwide,...
Highlights: DesignWare Controller and PHY IP for PCI Express and LPDDR accelerates development of the advanced data flow processor-based SoC Embedded Memories and Logic Libraries offer options for...
MOUNTAIN VIEW, Calif., Oct 23, 2019 Highlights: Astera Labs' Aries Smart Retimer is the industry's first 32GT/s retimer SoC designed to the PCIe 5.0 specification. It doubles the signal reach and...
Highlights: Synopsys ARC VPX5 and VPX5FS DSP Processors are based on an extended instruction set and VLIW/SIMD architecture optimized for highly parallel processing Multiple vector floating-point...