Cloud native EDA tools & pre-optimized hardware platforms
All News Releases
Su | Mo | Tu | We | Th | Fr | Sa |
---|---|---|---|---|---|---|
Su | Mo | Tu | We | Th | Fr | Sa |
---|---|---|---|---|---|---|
Highlights: Samsung certified Synopsys Fusion Design Platform for 5LPE process technology using 64-bit Arm Cortex-A53 and Cortex-A57 processors Fusion Design Platform redefines conventional design...
Highlights: DesignWare IP portfolio for GLOBALFOUNDRIES 12LP FinFET process includes Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters...
Highlights: Smart Loading technology in Verdi, enabled by Unified Compile with VCS, delivers 5X faster design load and tracing Unified constraint solver technology in VC Verification IP enables 2X...
Synopsys, Inc. (Nasdaq: SNPS) today announced that Astera Labs successfully utilized Synopsys' Fusion Design Platform™, Verification Continuum™ Platform, and Design Services to develop its...
Synopsys, Inc. (Nasdaq: SNPS) today announced that Trac Pham, CFO, will speak at the Baird 2019 Global Consumer, Technology and Services Conference in New York, on June 4, 2019, at the...
Highlights: Exceptional QoR delivered by IC Compiler II with Advanced Fusion technologies enables Juniper to meet aggressive PPA goals for next-generation networking designs Advanced Fusion...
Highlights: Patented full-chip-scale parametric design yield analysis delivers accurate statistical yield with over 1000X faster performance than Monte Carlo static timing analysis Unique design...
Highlights: Synopsys' Fusion Design Platform enables faster implementation with optimized PPA for Arm processors QuickStart Implementation Kit (QIK) using Arm Artisan Physical IP and POP IP,...
Highlights: Synopsys Cloud Solution now supports Google Cloud Platform for TSMC OIP VDE TSMC has certified that GCP meets both its stringent security and performance requirements Synopsys and...
Highlights: VC Formal Datapath Validation application delivers over 100X speed-up in formal verification between a reference C/C++ algorithm and RTL design implementation over conventional techniques