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Highlights: DesignWare STAR Memory System's full suite of test, repair, and diagnostic capabilities for embedded MRAM optimize test time without sacrificing test coverage New configurable memory...

Highlights: SpyGlass DFT ADV provides ISO 26262 Single Point Fault Metric (SPFM) calculation based on the effects of soft errors Fast static analysis at the RTL- or gate-level ensures minimum...

Highlights: New test points reduce manufacturing test costs by an average of forty percent and increase defect coverage Test Fusion delivers significant reduction in test point silicon area and...

Highlights: Industry's first LPDDR5 controller, PHY, verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations Complete DDR5 IP solution...

Highlights: FineSim SPICE 2018.09 delivers 3X faster runtime for analog circuits, adds RF analysis features Custom Compiler's Extraction Fusion with StarRC provides early parasitics for accurate...

Highlights: New Extraction Fusion and DRC Fusion technologies enable tighter design/layout collaboration and fewer late-stage design iterations Visually-assisted automation proven to deliver 2-10X...

Highlights: 3X performance advantage over existing solutions significantly reduces verification time New RF-class analysis capabilities to support high-frequency analog circuits Ideally suited for...

Synopsys, Inc. (Nasdaq: SNPS) today announced that it was selected by the Defense Advanced Research Projects Agency (DARPA) for the Posh Open Source Hardware (POSH) program to create new...

Highlights: Early adopters of Arm Neoverse IP, including next-generation "Ares" processor, have successfully taped out using Synopsys' Design Platform with Fusion Technology QuickStart...

Highlights: Synopsys' ASIP Designer tool automates the design of application-specific instruction set processors (ASIPs) and programmable accelerators Unique "compiler-in-the-loop" feature enables...