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Jun 4, 2019

Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process

High-quality DesignWare Interface and Analog IP Optimized for High Performance and Low Power in AI, Cloud Computing, and Mobile SoCs

Highlights: DesignWare IP portfolio for GLOBALFOUNDRIES 12LP FinFET process includes Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters...
May 30, 2019

Synopsys Extends Leadership with Enhanced Verification Continuum Platform

New Native Tool Integrations Enable up to 5X Higher Verification Performance

Highlights: Smart Loading technology in Verdi, enabled by Unified Compile with VCS, delivers 5X faster design load and tracing Unified constraint solver technology in VC Verification IP enables 2X...
May 30, 2019

Synopsys Design and Verification Solutions Enable Astera Labs to Develop Industry's First PCIe 5.0 Retimer SoC

Industry's First Full-chip Implementation and Verification Completed Entirely on Amazon Web Services Cloud

Synopsys, Inc. (Nasdaq: SNPS) today announced that Astera Labs successfully utilized Synopsys' Fusion Design Platform™, Verification Continuum™ Platform, and Design Services to develop its...
May 28, 2019

Synopsys CFO Trac Pham to Speak at Baird Global Consumer, Technology and Services Conference

Synopsys, Inc. (Nasdaq: SNPS) today announced that Trac Pham, CFO, will speak at the Baird 2019 Global Consumer, Technology and Services Conference in New York, on June 4, 2019, at the...
May 28, 2019

IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks

Juniper Networks Achieves 14% Lower Power and 6% Smaller Area on Next-generation Networking Design

Highlights: Exceptional QoR delivered by IC Compiler II with Advanced Fusion technologies enables Juniper to meet aggressive PPA goals for next-generation networking designs Advanced Fusion...

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