MOUNTAIN VIEW, Calif., Feb. 13, 2020 /PRNewswire/ --

Highlights:

• DesignWare ARC IoT Communications IP Subsystem integrates a low-power ARC EM11D Processor for efficient RISC and DSP performance, critical for addressing low-bandwidth communication needs for IoT applications
• Integrated hardware accelerators boost performance of application-specific kernels with minimal impact to silicon area
• Configurable digital front-end easily interfaces with RF wireless transceivers

Synopsys, Inc. (Nasdaq: SNPS) today launched its new DesignWare^® ARC^® IoT Communications IP Subsystem, an integrated hardware and software solution that combines Synopsys' DSP-enhanced ARC EM11D processor, hardware accelerators, dedicated peripherals, and RF interface to deliver efficient DSP performance for ultra-low bandwidth wireless IoT (NB-IoT) applications, such as machine to machine communication.

The ARC IP Subsystem includes SPI and GPIO for RF control and UARTs for logging and host control. The digital front end (DFE) offers a flexible interface to third party RF solutions, such as Palma Ceia's Release 14-compliant NB-IoT transceiver. The ARC IP Subsystem also contains a base software communications library, peripheral drivers, and application examples. The ARC IP Subsystem delivers the performance efficiency needed for a wide range of IoT applications including smart city, smart agriculture, and industrial automation.

"Smart IoT applications demand the robust and reliable data transfer with low power consumption to increase battery life," said Roy E. Jewell, chief executive officer of Palma Ceia SemiDesign. "The combination of Palma Ceia SemiDesign's LTE Cat NB1/NB2 Release 14 RF transceiver with Synopsys' ARC IoT Communications IP Subsystem provides designers with an efficient end-to-end solution for the rapid deployment of their wireless NB-IoT applications."

The integrated, ultra-low power ARC EM11D processor combines RISC and DSP capabilities for a flexible architecture that quickly adapts to rapidly changing wireless standards. The EM11D's zero-latency XY memory architecture implements instruction level parallelism and single-cycle 16+16 MAC operations for power-efficient data processing. Dedicated hardware accelerators for Viterbi decoding and trigonometric functions provide performance boosts for LTE NB-IoT algorithms while keeping processor frequency requirements to a minimum. Power management, critical to efficient IoT communications, is supported by an on-board power management unit, enabling up to six independent power domains and three unique power modes to support LTE Power Saving Mode (PSM) and Extended Discontinuous Reception (eDRX) modes.

The ARC IoT Communications IP Subsystem includes a baseline communications library, which provides a critical foundation for NB-IoT functions, such as symbol interpolation, FFTs, modulation, and data manipulation. The application examples demonstrate use-cases in a typical Orthogonal Frequency-Division Multiplexing (OFDM) processing chain. The subsystem is supported by Synopsys' DesignWare ARC MetaWare Toolkit, which includes a rich library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.  

"Emerging NB-IoT applications require extremely low-power and low-cost implementations that can quickly adapt to evolving wireless standards," said John Koeter, senior vice president of marketing for IP at Synopsys. "Synopsys' DesignWare ARC IoT Communications IP Subsystem with Palma Ceia SemiDesign's RF Transceiver provide a complete hardware and software solution, enabling designers to efficiently incorporate key NB-IoT communication functionality into their IoT devices with significantly less risk and effort."

Availability and Resources

• The DesignWare ARC IoT Communications IP Subsystem is available now from Synopsys
• PCS's LTE Cat NB1/NB2 Release 14 RF transceiver is available now from Palma Ceia SemiDesign. Learn more at: https://www.pcsemi.com/products/nb-iot/

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit https://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
Kelly James
Synopsys, Inc.
650-584-8972
kellyj@synopsys.com

SOURCE Synopsys, Inc.