Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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May 29, 2007IC Compiler Helps NEC Electronics Achieve 2X Performance Improvement While Meeting Power Budget
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May 29, 2007Enhanced Flow Uses Synopsys' IC Compiler and DC Topographical Technology to Manage Leakage for 65-Nanometer and Below Processes
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May 29, 2007Springer Book Explains How to Ease Adoption of Aggressive Power Management Techniques
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May 25, 2007IC Compiler Exceeds Target Performance While Lowering Project Cost
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May 24, 2007Single GDSII, Multi-Foundry Connectivity IP Enables Designs Using Common Platform Processes
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May 24, 2007Companies Leverage Unique Core Competencies to Further Hardware-assisted ASIC Verification
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May 17, 2007Topographical Technology Cuts Design Cycle and Chip Area for EXILIM Digital Camera IC
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May 17, 2007Synopsys DFT MAX Chosen as a Key Ingredient of a Cost-Effective Test Strategy
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May 17, 2007DesignWare IP Lowers Integration Risk and Drives Interoperability for Next Generation PCI Express Designs
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May 16, 2007Reduces Design Cycle Time by 30 Percent
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May 15, 2007Silicon-Proven DesignWare USB 2.0 nanoPHY Enables Designers to Reduce Risk and Speed Time-to-Market
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May 14, 2007Chinese-Language Edition of the Verification Methodology Manual (VMM) for SystemVerilog to Be Published by Beihang Press
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May 9, 2007New Lab Dedicated to World-Class Electronic Design Academics and Advanced Bioengineering Research
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May 7, 20075% Correlation Between Synthesis and Layout Key to Predictable ASIC Design Flow
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Apr 26, 2007DesignWare WiUSB IP Demonstrates Automated Configuration, Firmware Flexibility and Low Gate Count with Maximized Power Savings
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Apr 25, 2007Increased Portfolio Breadth Helps Simplify Subsystem Integration
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Apr 23, 2007Markus Levy, President of EEMBC and the Multicore Association, Will Deliver Keynote Address
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Apr 17, 2007Topographical Technology Delivers Early Predictability for Designs Utilizing Advanced Low-Power and Test Techniques
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Apr 17, 200735% Faster Runtime, Larger Capacity and Increased Automation Drive Designer Productivity
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Apr 17, 2007Joint Effort Targets Improved OPC Modeling Accuracy, Reduced Time to Model and Enhanced Model Predictability
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Apr 16, 2007Saber Simulator Selected to Address Robust Mixed-Signal, Multi-Domain Analysis and Verification Requirements
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Apr 11, 2007Aart de Geus and NASA Principal Scientist Steve Squyres Address Nearly 1,600 Engineers at Seventeenth Annual User's Conference
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Apr 10, 2007Collaboration Delivers OCP-Compliant Verification Solution for Improved Interoperability and Quality of OCP designs
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Apr 5, 2007Complete 65-Nanometer Design Flow Recognized as Common Platform Technology Critical Success Factor
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Apr 4, 2007New Features Assure Library Quality and Reduce Characterization Cost
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Apr 4, 2007Liberty NCX Accelerates Delivery of Production-Quality Current-Source Libraries
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Apr 2, 2007New FastSPICE Simulation Technology Enables SPICE Accuracy with FastSPICE Performance
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Mar 30, 2007
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Mar 29, 2007UPF Compliance Will Minimize Risk and Improve Designer Productivity
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Mar 29, 2007CCS Models Significantly Improve Accuracy for 65-nm and Below Semiconductor IP
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Mar 28, 2007Flow Delivers a 5-10X Boost in Productivity for Mobile and Consumer Applications
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Mar 28, 2007Awards Bestowed at ISQED's Eighth Annual Quality Symposium
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Mar 27, 2007Higher Performance for Multi-Mode Designs Drives Selection
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Mar 27, 2007Comprehensive Implementation, System-Level and Verification Solutions Speed Time-to-Market for STi7200 Dual-Video-Stream Device
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Mar 19, 2007TetraMAX Diagnostics Now Key Ingredient of Yield Learning Systems for Nanometer Processes
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Mar 13, 2007Verification Suite Enables Measurement of Device Parameters at Advanced Technology Nodes
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Mar 7, 2007Synopsys PrimeTime and Star-RCXT Solutions Deployed at Fujitsu as Standard for 65-Nanometer Sign-OffExtends Usage of Gold Standard Sign-off Solutions to 65-nm ASIC and COT Design Flows
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Mar 7, 2007analogZONE Recognizes High Performance and Low Power Capabilities for an Optimized, Silicon-proven Solution
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Mar 6, 2007DFT MAX Reduces Test Data Volume and Test Application Time for High-Quality Testing
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Mar 6, 2007Latest CCS-based Libraries Improve Designer Productivity for Low-Power, High-Performance Designs
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Mar 5, 2007Next-Generation VMM Solution Adds Verification Planning, Applications, and Automation to Proven VMM Methodology
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Feb 27, 2007Optimized x86-64 Hardware Offers Superior Price/Performance for OPC Compared to Custom Hardware Platforms
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