Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
-
Jan 31, 2007SPEF Extension Provides Consistent and Accurate Representation of Parasitic Sensitivity Information at 65 Nanometers and Beyond
-
Jan 29, 2007Synopsys to Directly License Foundry-Portable PowerPC Cores
-
Jan 24, 2007Key Technology Donated to Further OSCI Standard's Evolution
-
Jan 16, 2007DFT MAX Reduces Test Data Volume, Enables Higher-Quality Production Testing
-
Jan 15, 2007Unique LCD Driver Verification Solution Cuts Design Margin by 50 Percent
-
Jan 9, 2007Synopsys' Galaxy Design Platform Validated With Multi-Vdd Capability for UMC's 90-nm Process
-
Jan 9, 2007Ease of Migration, Strong Technology Roadmap Drive Competitive Selection
-
Jan 8, 2007Synopsys SystemVerilog Solution Used to Verify Next-Generation On-Chip Interconnect Infrastructure for Networking, Peripheral and Consumer Applications
-
Jan 3, 2007Orders Magma to Transfer Title of Fixed Timing Patents to Synopsys
-
Dec 13, 2006New Book Teaches Techniques to Develop an Effective SVA-Based Verification Strategy
-
Dec 11, 2006Enhanced STARCAD-CEL Methodology Accelerates Time-to-Market for Major Japanese Semiconductor Companies
-
Dec 4, 2006Synopsys Galaxy Design Platform and PrimeRail Deliver Complete Flow for Multi-threshold CMOS Design
-
Nov 21, 2006Builds Electronic Design Automation Industry's First Supercomputer to Claim 242nd Spot on Top500 List
-
Nov 21, 2006Simple Implementation and Predictable Results Were Key Drivers in Selection
-
Nov 20, 2006Combination of Design and Verification Platforms With DesignWare® IP Meets Tight Area, Power and Performance Goals
-
Nov 20, 2006Freescale Deploys VCS Native Testbench for SystemVerilog-Based Verification
-
Nov 7, 2006IC Compiler Enables 10 Percent Die-Size Shrink and 2X Faster Turnaround Time
-
Oct 31, 2006San Jose Mercury News High-Tech Journalist to Present Keynote
-
Oct 30, 2006Complete Solution Will Include Memory Controller and Mixed-Signal PHY to Reduce Risk and Speed System Integration
-
Oct 25, 2006Bridge Connects a Wealth of PCI Express Technology-Based Systems and Peripherals to AMBA 2.0 AHB Protocol-Based Designs
-
Oct 24, 2006Link Will Help Accelerate Yield Ramp of High-Volume Production ICs
-
Oct 23, 2006Comprehensive Test Flow Links Galaxy Platform With STAR Memory System
-
Oct 19, 2006Tight Correlation Between Synthesis and Layout Reduces Time-to-Market
-
Oct 17, 2006Significant Improvement in the Quality of At-Speed Testing Expected from Test Pattern Generation Based on Precise Timing
-
Oct 17, 2006Expanded Collaboration Will Extend Saber Product Line Integration with UGS' NX MCAD and Teamcenter PLM Technology
-
Oct 16, 2006Innovative Process-Aware DFM Product Family Enables Designers to Reduce Process Variability Impact and Improve Design for Advanced Semiconductor Manufacturing
-
Oct 11, 2006Automated Power Network Prototyping Delivers Optimized Area and Layer Trade-offs
-
Oct 9, 2006University to Receive World-Class Laboratory to Advance Education in Microelectronics Design
-
Oct 9, 2006Synopsys JupiterXT and IC Compiler Tools Enable Die Size Optimization
-
Oct 4, 2006Next-Generation Signal Integrity Sign-off Models to Deliver Improved Accuracy and Reduced Turnaround Time
-
Oct 3, 2006SystemVerilog and the VMM Methodology Provide a Robust, Scalable Verification Environment
-
Oct 2, 2006Predictable Performance and Excellent Support Essential for Development of High-Performance Microdisplays
-
Sep 28, 2006Synopsys Recognizes Engineers' Technical Excellence With Best Paper Awards at SNUG Boston ConferenceMore Than 400 Engineers Gather at Eighth Annual Regional User's Conference
-
Sep 27, 2006Second Consecutive Runtime Improvement for TetraMAX Tool Offers Designers Substantial Productivity Benefits
-
Sep 25, 2006High-Performance Sitka Evaluation and Development Platform Allows Designers to Test and Debug Applications Using the DesignWare PCI Express IP in Hardware
-
Sep 20, 2006Solutions Target Improved Lithography Modeling Accuracy, Reduced Time-to-Silicon, and Improved Manufacturing Yield
-
Sep 19, 2006Technology Proven to Help Customers Achieve Ultra Low Power IC Designs
-
Sep 19, 2006PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
-
Sep 15, 2006Synopsys Dedicates Scan Chain Inventions to Public Domain
-
Sep 13, 2006Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups
Press Kit
About Us
Publications