MOUNTAIN VIEW, Calif., May 19 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced that Matsushita Electric Industrial Co., Ltd., the electronics company behind the globally recognized Panasonic brand, has signed an expanded EDA license agreement to establish Synopsys as its leading EDA supplier across the Semiconductor Company of Matsushita Electric Industrial Co., Ltd. (hereinafter called "Matsushita") design flow.
The expanded EDA license agreement calls for increased usage of tools throughout Synopsys' product portfolio, including the Synopsys Galaxy™ design platform featuring Design Compiler® synthesis, PrimeTime® timing analysis, and IC Compiler place and route technology, the Synopsys Discovery™ verification platform featuring the VCS® and HSIM® simulators for analog and digital verification, and Synopsys' design for manufacturing (DFM) portfolio including a mask synthesis solution. The collaborative arrangement in the license agreement includes a focused initiative to optimize the design flow speed and throughput for quality system-on-chip (SoC) development. This important joint initiative is designed to enable higher engineering productivity and keep Matsushita at the leading edge in semiconductor development and manufacturing.
Synopsys and Matsushita have a long history of working together. One example of a technology that was supported by this collaboration is Synopsys' new Design Compiler Graphical product, which extends topographical technology to predict, visualize and alleviate routing congestion. Matsushita is reporting early visibility and reduction of congestion when using Design Compiler Graphical, and the netlist it generates is easier to place and route in IC Compiler.
A new DFM-centric routing technology under development at Synopsys showcases another benefit of strong collaboration with Matsushita. In early trials, Matsushita has seen routing runtimes cut significantly by multi-threading support that takes advantage of the latest microprocessor multi-core architectures.
"We have established a close collaborative arrangement with Synopsys to master new challenges encountered at the leading edge of technology," said Hakuhei Kawakami, director at Corporate System LSI Division, Semiconductor Company, Matsushita Electric Industrial Co., Ltd. "Technical leadership in the Synopsys offering has already enabled Matsushita to successfully deploy design flows on deep submicron processes."
"By teaming up with Matsushita, we intend to accelerate delivery of more functionality while reducing power for consumer electronics products," said Aart de Geus, chairman and CEO of Synopsys, Inc. "In Matsushita we have a partner who has demonstrated sustained consumer electronics leadership for many years. As a direct result of our long-term and fruitful relationship, we are fortunate to count such a strong leader among the companies in close collaboration with Synopsys."
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
Safe Harbor Statement/Forward-Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits and availability of the DFM-centric routing technology. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, engineering difficulties, uncertainties attendant to any new product offering, and other risks as identified in the section of Synopsys' most recent Quarterly Report on Form 10-Q entitled "Risk Factors."
Synopsys, Design Compiler, Discovery, Galaxy, HSIM, PrimeTime and VCS are trademarks or registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
SOURCE: Synopsys, Inc.
CONTACT: Yvette Huygen, +1-650-584-4547, email@example.com, or
Investors, Lisa Ewbank, +1-650-584-1901, both of Synopsys, Inc.
Web site: http://www.synopsys.com/