Synopsys, Altera and TSMC Collaboration Delivers Industry-Leading 45-Nanometer Extraction Accuracy
Synopsys Star-RCXT Extraction Technology Files Silicon-Validated for TSMC 45-Nanometer Design Process
MOUNTAIN VIEW, Calif., Dec. 11 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the qualification and immediate availability of the Synopsys Star-RCXT™ parasitic extraction solution for TSMC's 45-nanometer (nm) process technology. This qualification is the result of collaboration between Synopsys, Altera and TSMC to develop and silicon-validate advanced modeling of key process variation effects that impact the performance of digital, analog and memory circuits. Altera, a pioneer in programmable logic, is now deploying Synopsys' Star-RCXT as the preferred extraction tool for its 45-nm design sign-off flow.
"We have successfully used Synopsys' Star-RCXT extraction tool on our 90-nanometer and 65-nanometer devices," said Eugene Chen, director of CAD Engineering at Altera Corporation. "Our recent collaboration on modeling advanced 45-nanometer process effects increases our confidence in the ability of the Star-RCXT solution to ensure the success of our next-generation devices as well. We have now standardized on the Star-RCXT solution for our 45-nanometer design flows on the merits of its sub-femtofarad accurate process modeling, its proven track record at each successive technology node and its seamless integration with our existing Synopsys sign-off solutions."
Synopsys, Altera and TSMC worked together to develop modeling specifications for two key 45-nm interconnect process effects-microloading and gate-to-contact coupling capacitance variation. TSMC and Altera validated that the Synopsys Star-RCXT solution provides accurate modeling of these and other 45-nm process effects caused by lithography variation, chemical-mechanical polishing (CMP), width-dependent temperature variation and dielectric damage in ultra-low-K process.
"TSMC and Synopsys collaborated early on to address 45-nanometer interconnect modeling of microloading effects and gate-to-contact capacitance variation," said Kuo Wu, deputy director of Design Service Marketing at TSMC. "The Synopsys Star-RCXT extraction tool has satisfactorily completed our qualification criteria to take full advantage of TSMC's leading 45-nm process technology with a high standard of model accuracy."
"The Star-RCXT solution's continued technology lead is the result of our long-standing collaboration with industry leaders such as TSMC and Altera," said Robert Hoogenstryd, director of Design Analysis and Sign-Off Marketing at Synopsys. "The 45-nanometer qualification and first-to-deploy success of Star-RCXT is yet further proof of our customers' confidence in the tool's ability to deliver silicon success for their most advanced designs."
Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading system and semiconductor design and verification platforms, IC manufacturing and yield optimization solutions, semiconductor intellectual property and design services to the global electronics market. These solutions enable the development and production of complex integrated circuits and electronic systems. Through its comprehensive solutions, Synopsys addresses the key challenges designers and manufacturers face today, including power management, accelerated time to yield and system-to-silicon verification. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys is a registered trademark of Synopsys, Inc. Star-RCXT is a trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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