Synopsys Announces Support for Galaxy Design and Discovery Verification Technology on Intel® Xeon™ Processor With the Intel® EM64T
Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, today announced that it is the first electronic design automation (EDA) software company to support the Intel® Xeon™ processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64- and 32-bit computing with the Red Hat Enterprise Linux version 3 operating system using its Galaxy™ design and Discovery™ verification technology. Synopsys' technology, running on Intel's Xeon processor architecture with Intel EM64T, delivers the high performance and increased capacity engineers need to design and verify today's complex system-on-chip (SoC) designs.
"We are pleased to see the release of Synopsys products on Intel's Xeon processor-based platforms, offering both 64-bit and 32-bit computing to meet the ever-increasing design computing capacity and performance needs," said Guru Bhatia, director of engineering computing, Intel Corporation. "The Intel Xeon processor-based platforms with Intel EM64T provide large memory support, Demand Based Switching for power consumption optimization, and PCI-Express-based advanced I/O along with higher performance. That combination of features and performance, coupled with Synopsys' suite of semiconductor design and verification tools, gives a technical advantage to the EDA engineering community to design complex silicon products."
As computational power, multi-media, graphics and communications features converge in consumer products, and as process technology shrinks to 90 nanometers and below, chip designers face new pressures. These pressures include design complexity and transistor counts in excess of 200 million. In addition, extreme sensitivities to cost, power consumption and chip size factor heavily in the design process. As a result, designers demand the best EDA tools and compute platforms to meet these challenges.
"Synopsys supplies industry-leading design and verification technology with support for underlying powerful compute platforms," said Karen Bartleson, director of interoperability at Synopsys. "We're addressing our customers' interest in the latest processor architecture from Intel by adding the new Xeon processor platform to our compute platforms roadmap."
Synopsys supports the following Galaxy and Discovery technologies on the new Intel Xeon processor-based compute platform: The Design Compiler® and DesignWare® Library arithmetic generators and building blocks used for synthesis, the DFT Compiler™ and TetraMAX® test, Physical Compiler® and Astro™ physical implementation, Power Compiler™ power management, PrimeTime® static timing analysis, Formality® equivalency checking, Hercules™ layout verification and NanoSim® mixed-signal design software. Additional products supporting this platform include: The BSD Compiler, Design Compiler FPGA, Design Analyzer™, HDL Compiler™, Module Compiler™ and PathMill® tools. Product support in March 2005 is expected to include VCS® complete RTL verification solution, with more product support planned for 2005.
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com/.
NOTE: Synopsys, Design Compiler, DesignWare, Formality, NanoSim, PathMill, Physical Compiler, PrimeTime, TetraMAX and VCS are registered trademarks of Synopsys, Inc. Astro, Design Analyzer, DFT Compiler, Discovery, Galaxy, HDL Compiler, Hercules, Module Compiler and Power Compiler are trademarks of Synopsys. All other products mentioned in this release are the intellectual property of their respective owners.
SOURCE: Synopsys, Inc.
CONTACT: Pierre Golde of Synopsys, Inc., +1-650-584-4194, or
firstname.lastname@example.org; or Suraya Akbarzad of Edelman Public Relations,
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Web site: http://www.synopsys.com/