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Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Altera, a pioneer in system-on-a-programmable-chip (SOPC) solutions, has deployed Synopsys' Star-RCXT™ extraction tool and HSIM™ FastSpice simulator for its FPGA design flow targeting TSMC's 65-nanometer (nm) Nexsys™ process technology. The Star-RCXT extraction tool offers advanced process modeling of 65-nm effects with accurate correlation to silicon, as well as seamless integration with HSIM simulator to achieve fast time-to-results.
"Adopting the Star-RCXT extraction tool for our 65-nm FPGAs is the logical choice given our successes with it on our 90-nm Stratix™ devices," said Eugene Chen, director of CAD Engineering at Altera. "We selected the Star-RCXT tool on the merits of its TSMC verification, its proven ability to model 65-nm effects with sub-femtofarad accuracy, and its seamless integration with Synopsys' HSIM FastSpice simulator."
The Star-RCXT tool is the market-leading parasitic extraction solution in Synopsys' Galaxy™ Design Platform, and the only extraction tool to cover cell-based, custom digital, and analog/mixed-signal designs. It supports 65-nm process capabilities including in-die process variation solutions such as selective process biasing (spacing- and width-dependent metal bias), local density effects, length of diffusion density and polynomial-based width-dependent thickness variation, width-dependent temperature variation, and metal fill. In modeling such advanced silicon process features, the Star-RCXT tool extracts silicon-accurate resistance capacitance (RC) parasitics for use with the HSIM FastSpice simulator to ensure rapid verification of custom digital designs.
"TSMC and Synopsys have a long, steady, and deep relationship," said Edward Wan, senior director of design service marketing at TSMC. "Synopsys' Star-RCXT extraction tool enables designers to take full advantage of TSMC's leading-edge foundry process for accurate modeling at 65-nm technology effects."
"Synopsys delivers proven design flows that enable designers to produce accurate designs using the most advanced silicon capabilities," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "With this proven foundry flow, Altera will deliver its next-generation devices to market with high predictability and yield."
Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including expectations of the timing of additional processor support for the ARM-Synopsys Reference Methodology (RM) using Synopsys' Design Compiler Topographical technology. These statements are based on current expectations and beliefs. Actual results could differ materially from these statements as a result of unforeseen difficulties in adapting the reference methodology to different processor platforms, uncertainties attendant to any new design flow or methodology and certain statements contained in the section of Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended January 31, 2006 entitled "Management's Discussion and Analysis of Financial Condition and Results of Operations -- Factors That May Affect Future Results."
NOTE: Synopsys is a registered trademark of Synopsys, Inc. Galaxy, HSIM, and Star-RCXT are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Janet Berkman Synopsys, Inc. 650-584-5707 email@example.com Tara Yingst Edelman 650-429-2731 firstname.lastname@example.org
SOURCE: Synopsys, Inc.
CONTACT: Janet Berkman of Synopsys, Inc., +1-650-584-5707, or
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Web site: http://www.synopsys.com/