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Synopsys' Pioneer-NTB SystemVerilog Testbench Automation Wins IEC DesignVision Award
SystemVerilog Testbench Automation Technology Awarded Top Honor in Design Verification Category
PRNewswire-FirstCall
MOUNTAIN VIEW, Calif.

Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that the Pioneer-NTB SystemVerilog testbench automation tool, a component of Synopsys' Discovery™ Verification Platform, was honored as the recipient in the design verification category in the annual International Engineering Consortium (IEC) DesignVision Awards program. This is the second year in a row that Synopsys has been recognized for its innovation and leadership in verification. The DesignVision Awards were announced at a ceremony that took place on Tuesday, February 7, 2006 at DesignCon, an educational conference and technology exhibition held in Santa Clara, CA. An industry panel, sponsored by the IEC, selected the Pioneer-NTB tool based on multiple criteria, including innovation, uniqueness, market impact and customer benefits. Pioneer-NTB enables verification teams to deploy Synopsys' advanced verification methodologies built on open industry standards in a VHDL, Verilog or mixed-language environment to find more bugs faster with increased productivity.

"The DesignVision Awards recognize innovative products and services that support the work of electronic design engineers, the core audience at DesignCon," said Barry Sullivan, DesignCon 2006 Program Director. "The IEC is pleased to provide this recognition to companies whose products exemplify our standard of service to the industry."

The Pioneer-NTB SystemVerilog testbench automation tool increases verification productivity and improves the quality of complex SoC and IP designs by enabling engineers to use advanced coverage-driven, constrained-random and assertion-based verification techniques. It allows engineers to take advantage of these proven verification technologies on third-party VHDL and Verilog simulators. The tool provides easy-to-use connections from its SystemVerilog verification environment to popular third-party simulators. By using Pioneer-NTB, verification engineers can adopt a single, standards-based, advanced verification infrastructure in mixed-simulation environments.

The Pioneer-NTB tool is built on Synopsys' proven VCS® and Vera® technology and takes advantage of the extensive ecosystems built around the solutions, including methodology, debug and analysis environments, assertion IP and verification IP. The tool fully supports the Verification Methodology Manual for SystemVerilog, enabling chip development teams to adopt the same best practices used by experts, resulting in more efficient and more thorough verification.

"As the industry leader in SystemVerilog design and verification, we are honored to see Synopsys' SystemVerilog testbench automation technology chosen for a DesignVision Award by the IEC," said George Zafiropoulos, vice president of Marketing, Synopsys Verification Group. "Pioneer-NTB demonstrates Synopsys' commitment to delivering industry leading SystemVerilog-based solutions to the market and provides users an efficient path away from proprietary legacy verification environments towards an industry standard SystemVerilog environment."

For more information on the Pioneer-NTB SystemVerilog testbench automation tool, visit www.synopsys.com/pioneer-ntb

About the DesignVision Award Program

In keeping with its 60-year mission of bringing the highest quality and most innovative forms of education to the industry, the IEC's DesignVision Awards recognize leading-edge products and services in the electronic design and semiconductor industries. The awards mirror a rich IEC tradition of recognizing innovative technology in the telecommunications field, another industry in which the IEC actively provides educational opportunities. Recipients of the DesignVision 2006 Awards were chosen based on innovation, uniqueness, market impact, customer benefits and value to society.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

NOTE: Synopsys, VCS and Vera are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

  Editorial Contacts:
   Isela Warner
   Synopsys, Inc.
   650-584-1644
   igamboa@synopsys.com

   Sarah Seifert
   Edelman
   650-968-4033
   sarah.seifert@edelman.com

SOURCE: Synopsys, Inc.

CONTACT: Isela Warner of Synopsys, Inc., +1-650-584-1644, or
igamboa@synopsys.com; or Sarah Seifert of Edelman, +1-650-968-4033, or
sarah.seifert@edelman.com, for Synopsys

Web site: http://www.synopsys.com/