Synopsys, Inc. Announces Technical Seminar Series Featuring Verification, Implementation, and Design-For-Manufacturing Solutions
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced the commencement of its annual technical seminar series. From systems to silicon, Synopsys provides solutions that address the most difficult challenges confronting engineers pushing IC design to the limit.
WHAT: The Synopsys SpringTech 2005 Seminars are a forum for members of
the electronic design automation and manufacturing community to learn how
to increase engineering productivity, design quality and silicon volume
using Synopsys' proven methodologies and solutions. Intended for design,
verification and process engineers and managers, these free, in-depth
technical events focus on functional verification, implementation and
design for manufacturing.
WHEN: Beginning March 8, 2005. Dates and times vary worldwide.
WHERE: Worldwide locations include: Asia-Pacific, Canada, Europe, Japan
and the USA.
WHO ATTENDS: Design, verification and process engineers and managers.
The Discovery™ Verification Platform Series
Finding More Bugs Faster with Proven Verification Methodologies
As verification challenges continue to grow faster than chip complexity, new methodologies and higher verification throughput must be used to help ensure first-pass silicon and time-to-market success. The seminars feature proven verification methodologies that help customers find more design bugs faster and address the growing challenge of verifying today's complex designs. The seminars span the system, chip and block levels and cover Synopsys' proven Reference Verification Methodology, including assertion-based and coverage-driven techniques, VCS® Native Testbench and DesignWare® verification IP. In addition, a proven, mixed-signal verification methodology will be presented that addresses the complex problems associated with today's systems-on-chips. Janick Bergeron, Synopsys Scientist, will be a guest speaker at certain seminar locations.
The Galaxy™ Design Platform Series
The Fastest Path to Successful Silicon at 130nm, 90nm and Beyond
This seminar series features proven methodologies for the fastest path to silicon at 130nm and for successful transition to 90nm and beyond. Topics include proven techniques for yield optimization, achieving lower power and higher performance. Go-deep sessions will show designers how to get the best results with RTL synthesis, physical implementation, sign-off, and test. Certain locations will include a demonstration of advanced multi-voltage techniques utilizing the ARM® Intelligent Energy Manager™ (IEM) implemented in a reference design developed jointly by ARM and Synopsys.
These seminars will show how Synopsys' DFM product family addresses critical manufacturability issues for 65-nm and below designs with its highly scalable, high-accuracy and yield-enhancing solutions. Attendees will get an overview on the importance of a comprehensive tool suite, and will be able to select a breakout session on each design stage, including mask synthesis, mask data prep, physical verification, lithography verification and TCAD.
HOW TO REGISTER: For more information and to register, visit http://www.synopsys.com/links/seminars.html?BAC-springtech05&Link=SNPS_PR .
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .
NOTE: Synopsys, DesignWare, and VCS are registered trademarks and Discovery and Galaxy are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Contact: Eileen Hunt of Synopsys, Inc., +1-650-584-5374, or firstname.lastname@example.org.
PRNewswire -- March 3
SOURCE: Synopsys, Inc.
Web site: http://www.synopsys.com/