HHNEC Standardizes on Synopsys' Proteus OPC Software to Reduce Mask Synthesis Turn-Around-Time
Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, and Shanghai Hua Hong NEC Electronics Limited (HHNEC), today announced HHNEC's adoption of Synopsys' Proteus optical proximity correction (OPC) software. HHNEC is a joint venture between NEC Corporation, Jazz Semiconductor and Shanghai Hua Hong Group, and is one of the leading 8-inch semiconductor foundries in China. HHNEC selected Proteus to increase accuracy, decrease mask synthesis turn-around-time and obtain higher yields through the utilization of Proteus' unique scalable architecture.
"Using Proteus OPC increases our critical dimension accuracy and ability to manufacture high yield chips with quick turn around time for our demanding customers," said Dr. Lei Ping Lai, Chief Marketing and Technology Officer, HHNEC. "Synopsys offers comprehensive mask synthesis solutions that offer reliable and fast results for our manufacturing needs."
As process node size decreases, the processing time for OPC increases. Proteus' unique distributed processing architecture provides near-linear scalability that allows customers to reduce turn-around-time by using clusters of inexpensive Linux-based CPUs. This scalability makes Proteus attractive for future, smaller geometries of semiconductor designs.
"The adoption of Proteus by HHNEC is another example of a leading semiconductor company selecting Proteus for its scalable architecture and high accuracy required by small process geometries," said Edmund Cheng, vice president of marketing for DFM at Synopsys. "Synopsys continues to solve the growing manufacturing and production issues by offering the most comprehensive design-for-manufacturing (DFM) solutions in mask synthesis, mask data preparation, TCAD and lithography verification."
About Synopsys DFM
Synopsys offers the industry's most comprehensive RTL-to-Mask DFM solution. Its DFM product family addresses critical yield and manufacturability issues with its Proteus® mask synthesis, CATS™ mask data preparation, SiVL® lithography verification, iVirtual Stepper™ mask defect dispositioning and Taurus™ TCAD software products. Synopsys leverages this expertise through its industry-leading Galaxy™ design platform implementation solution in order to help ensure that designs at 90-nm and smaller geometries will meet key manufacturing requirements. Synopsys' DFM product family is the solution-of-choice for 130-nm yield sensitive, high-value chips, worldwide. Eighty percent of all sub-180-nm microprocessors, 50 percent of all sub-180-nm DRAMs, 80 percent of all sub-180-nm FPGA and graphics chips, and 75 percent of all sub-180-nm cellular baseband chips produced use Proteus, and more than 80 percent of all photomasks produced use CATS.
Shanghai Hua Hong NEC Electronics Limited (HHNEC) is the first 8" wafer foundry provider in Mainland China with state-of -the-art CMOS Process technology, manufacturing equipment and ISO certification (both 9001 and 14000) and, BS7799 qualified service support system. Founded on July 17th, 1997, HHNEC is a joint venture of Shanghai Hua Hong Group and NEC Corporation, with a registered capital of US$700 million and a total investment of US$1.2 billion, and is known as the core of "National 909 Project". In November 2003, Jazz Semiconductor and Hua Hong International contributed their investment for HHNEC, which increased the registered capital to US$789.41 million. HHNEC serves as the wafer Foundry provider for customers from both abroad and domestic China. Its production capacity will be extended to be 42,000 wafers/month using 0.18µm process technology by the end of 2004. For more information, please visit www.hhnec.com
Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems on chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
The statements made in the sections entitled "About Synopsys DFM" and "About Synopsys" are made only by Synopsys and the statements made in the section entitled "About HHNEC" are made only by HHNEC. Synopsys is a registered trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
SOURCE: Synopsys, Inc.
CONTACT: Jennifer Scher of Synopsys, Inc., +1-650-584-5594, or
firstname.lastname@example.org; or Sarah Seifert of Edelman, +1-650-429-2776, or
email@example.com, for Synopsys, Inc.; or Tan Ping of HHNEC,
+86 (21) 5031-0909, ext. 4571, or firstname.lastname@example.org
Web site: http://www.hhnec.com/
Web site: http://www.synopsys.com/