Renesas Technology Uses Synopsys' Galaxy Design Platform to Tape Out a 90-Nanometer Production Design
Design for Yield Capabilities Enable Renesas Technology to Achieve Yield Goals in Wireless SoC
Synopsys Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Renesas Technology Corp., a world-class supplier of semiconductors, has taped out a 90-nanometer (nm) system-on-chip (SoC) design for wireless applications using Synopsys' Galaxy™ Design Platform. Synopsys' physical design solution -- with advanced design for yield (DFY) capabilities in the Astro™ product -- enabled Renesas Technology to meet their yield goals in this 90-nm production design.
"With this being our 90-nanometer wireless design, we were concerned about DFM issues," said Teruaki Harada, Department Manager of DFM & EDA Technology Development Dept., Design Technology Division, Renesas Technology Corp. "The yield enhancement techniques in Synopsys' Galaxy Design Platform, particularly the Astro product's ability to insert redundant vias and efficiently enforce antenna rules, helped us significantly optimize our design and achieve our 90-nm yield targets."
The Renesas Technology multimillion gate design was created using Synopsys' physical design solution -- the Design Compiler® product for synthesis, the Power Compiler™ product for dynamic and leakage power optimization, the Physical Compiler® and Astro products for physical implementation, and the Star-RCXT™ product for full-chip parasitic extraction. The yield-aware routing optimization techniques in the Astro product -- such as redundant via insertion -- helped Renesas Technology minimize impact on timing-critical nets and optimize for yield while maintaining a predictable convergence to timing closure.
"Synopsys is working closely with semiconductor vendors to deliver comprehensive yield-enhancement strategies," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Companies such as Renesas Technology turn to Synopsys as their vendor of choice for physical design when they need advanced design for yield techniques to meet their yield goals and deliver cost-effective chips on time."
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/..
NOTE: Synopsys, Design Compiler and Physical Compiler are registered trademarks of Synopsys, Inc., and Galaxy, Astro, Power Compiler, and Star-RCXT are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
SOURCE: Synopsys, Inc.
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