Press Releases

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  Jan 28, 2021

  Synopsys Demonstrates Silicon Proof of DesignWare 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs

  DesignWare IP With Unmatched Long-Reach Performance Results Supports Insertion Loss Greater Than 40dB and Delivers Power-Efficiency of Less Than five pJ/Bit

  • Photos 1
• Jan 27, 2021

  Synopsys Delivers Industry's First Integrity and Data Encryption Security IP Modules for PCI Express 5.0 and Compute Express Link 2.0 Specifications

  DesignWare IDE Security IP Modules Protect Against Data Tampering and Physical Attacks in High-Performance Cloud Computing SoCs
• Jan 19, 2021

  Sondrel Selects Synopsys Fusion Design and Verification Platforms to Displace Legacy Design Tools

  Sondrel Accelerates SoC Design and Packaging with Synopsys Solutions
• Jan 12, 2021

  Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs

  Collaboration Builds on Successful Adoption of Broad DesignWare IP Portfolio in Socionext's High-Performance AI Engine and Accelerator Solution
• Jan 12, 2021

  Synopsys and Socionext Expand Collaboration to Deploy HBM2E IP for 5-Nanometer Process in AI and High-Performance Computing SoCs

  Collaboration Builds on Successful Adoption of Broad DesignWare IP Portfolio in Socionext's High-Performance AI Engine and Accelerator Solution

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