Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Mar 27, 2006
Enhanced STARCAD-21 RTL-to-GDSII Production Flow Ready for Deployment at Major Japanese Semiconductor Companies
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Mar 22, 2006
Galaxy Design Platform Delivering Predictable Time-to-Results Through Sign-off Correlation to Silicon
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Mar 21, 2006
Processor Implementation and Verification Enabled by Powerful Tools From Synopsys' Galaxy and Discovery Platforms
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Mar 20, 2006
More Than 150 Companies Worldwide Have Adopted Synopsys' SystemVerilog Solutions to Create Today's Hottest Electronics Products
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Mar 20, 2006
VCS Verification Library Enables Rapid Adoption of SystemVerilog With Full Support of the Verification Methodology Manual (VMM) for SystemVerilog
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Mar 15, 2006
Sign-Off Flow With Star-RCXT Delivers High Predictability
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Mar 8, 2006
DesignWare® Library Core's Portability and Accessibility Cited by IBM in Award Presentation
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Feb 27, 2006
Production-Ready Environment Integrates Proven RTL-to-GDSII Flow With New Utilities to Improve Design Productivity and Tapeout Predictability
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Feb 27, 2006
Flow Supports IC Compiler for Common Platform's Low-Power Process
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Feb 22, 2006
IEEE Working Group Chairman Awards and Certificates of Recognition Presented to Synopsys Engineers
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Feb 15, 2006
Synopsys Galaxy Design Platform Delivers Complete Flow for Ultra-Low-Power Design
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Feb 8, 2006
SystemVerilog Testbench Automation Technology Awarded Top Honor in Design Verification Category
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Feb 6, 2006
Enables Longer Battery Life and Lower Cost for Mobile and High-Volume Consumer Products
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Jan 25, 2006
Japanese-Language Edition of the Manual to Be Published by CQ Publishing
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Jan 24, 2006
Synopsys Is First to Deliver PCI Express Gen II Digital IP for Increased Bandwidth in Networking, Embedded and Computer Applications
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Jan 10, 2006
IP-Enabled Services Firm Joins Synopsys' SystemVerilog Catalyst Program
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Dec 19, 2005
AMCC Deploys SystemVerilog Verification Environment With Synopsys' VCS® Native Testbench and Reference Verification Methodology
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Dec 19, 2005
PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
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Dec 14, 2005
Provides Complete Set of Standards-Based I/O Libraries for General Purpose and High-Performance Applications
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Dec 7, 2005
DesignWare PHYs for Hi-Speed USB 2.0 and Hi-Speed USB OTG Developed with TSMC's Production-Proven 90-nm Libraries
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Dec 6, 2005
Increased Predictability of Manufacturing Process through TCAD Lowers Product Development Cost and Time
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Nov 28, 2005
IC Compiler Fits Easily in the Agere Flow, Delivers Higher Performance
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Nov 21, 2005
Reference Design Flow Features Low Power Management and Design-for-Manufacturing Automation Capabilities
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Nov 8, 2005
TetraMAX® ATPG Performance Speedup Combined with a New Waveform Debugger Streamline Test Pattern Generation for Complex Designs
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Nov 7, 2005
Composite Current Source Model First to Combine Timing, Noise and Power
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Nov 7, 2005
Designers Benefit from Enhanced Productivity and Reduced Design Margins
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Nov 2, 2005
Combined Technology Can Read, Write and Provide On-The-Fly View of Compressed Files
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Nov 1, 2005
DFT MAX Achieves 90% Test Data Volume Reduction for Flat Display TV Controller
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Oct 31, 2005
Exar Develops and Deploys Advanced SystemVerilog Verification Environment and Reference Model with VCS® Native Testbench Technology
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Oct 24, 2005
TetraMAX Diagnostics Enable TSMC to Accelerate Yield Ramp on Deep Submicron Designs
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Oct 19, 2005
Advanced Testbench Techniques Critical for Multi-Protocol Verification Environment at Chip and System Levels
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Oct 19, 2005
Project Methodology Leverages Assertions, Functional Coverage, Constrained-Random Stimulus Generation and PCI Express® Verification IP
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Oct 17, 2005
Sentaurus Sets New Standard in TCAD Simulation Capabilities for Semiconductor Process, Device, Circuit and System Analysis, and Parametric Yield Optimization
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Oct 10, 2005
Communications Leader Uses Synopsys' Tools and Flows From Design Through Physical Implementation
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Oct 4, 2005
ARM and Synopsys Collaborate to Demonstrate Galaxy Design and Discovery Verification Flow for ARM Cortex-A8 Processor Implementation
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Oct 4, 2005
Comprehensive Design Kit for X-FAB's 0.6-Micron Process Improves Quality and Speeds Time to Market
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Oct 4, 2005
Accurate OPC Modeling Critical for Accelerating Time to Yield
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Oct 3, 2005
New, Accurate Model Speeds Time to Results by 2X
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Oct 3, 2005
Acquisition Will Establish EDA Industry's First Direct Connection into Fabrication Processes
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Oct 3, 2005
Enhanced Reference Methodology delivers 10 percent higher performance
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Oct 3, 2005
Synopsys and Dassault Partner to Provide Improved Electro-Mechanical Design
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Sep 26, 2005
Mixed -Signal IP Complements Synopsys' Market-Leading Portfolio of Serial Interface Controllers
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Sep 26, 2005
Verification IP Product Combines with Advanced Methodologies and Tools to Deliver a High-Performance Integrated Verification Environment
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Sep 26, 2005
Testing Conducted With Synopsys' Wireless USB Device Controller IP and Alereon's WiMedia Ultra-Wideband PHY
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Sep 26, 2005
Companies Lead Industry With Hardware and Software Interoperability Testing
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Sep 26, 2005
Early IP Availability From Synopsys Drives Wireless USB Integration Into Next Generation SoCs
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Sep 26, 2005
Pioneer-NTB Delivers Standards-Based, Mixed-HDL Verification Built on Synopsys' Proven VCS® Technology
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Sep 21, 2005
Automated Macro Placement and Power Network Synthesis Reduces Design Planning Time Up to 10x
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Sep 21, 2005
Verification Effort Reduced With Certified DesignWare Verification IP
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Sep 21, 2005
New ARM-Synopsys Book Provides Blueprint for System-on-Chip Verification Success Using SystemVerilog
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Sep 21, 2005
Addition Enables Easy Adoption of AMBA 3 AXI Protocol with Automated Subsystem Assembly and Comprehensive Set of Synthesizable and Verification IP
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Sep 21, 2005
VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog
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Sep 19, 2005
Leading-Edge Companies Achieve Significant Productivity Gains and Cost Savings Using New Flip Chip Methodology
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Sep 14, 2005
Syracuse to Receive Sun Workstations and Synopsys EDA Software and Licenses
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Sep 14, 2005
Dismissal Resolves Litigation With No Additional Expense to Synopsys
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Aug 23, 2005
Demo at Intel Developer Forum Shows Two-Way Transfer of Large Multimedia Files using the USB-IF's Wireless USB and WiMedia UWB Platform
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Jul 27, 2005
ASIC and System Developer Adopts Synopsys' Discovery™ Verification Platform for 90-Nanometer Chip
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Jul 19, 2005
Latest Flow for 0.13-micron Process Offers Advanced Floor Planning, Signal Integrity and Reliability Features
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Jul 12, 2005
New Specification Targets Increasing File Size, Need for Common Data Format
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Jun 27, 2005
Design for Yield Capabilities Enable Renesas Technology to Achieve Yield Goals in Wireless SoC
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Jun 22, 2005
Comprehensive Built-in Coverage Metrics in Synopsys' VCS® Solution Increase Verification Quality for STMicroelectronics' 90 Nanometer HDTV Processor Chip
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Jun 21, 2005
Semiconductor Industry Executives Reflect on 40th Anniversary of Moore's Law
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Jun 15, 2005
Collaboration on Interoperable Design Solutions to Benefit User Community
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Jun 14, 2005
Galaxy Platform Enables 50 Percent Power Savings in SoC Design
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Jun 14, 2005
ARM, TSMC, Virage Logic and Library Technologies Gear Up to Support CCS-enabled 90nm Libraries
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Jun 10, 2005
Scalable Distributed Processing Reduces Physical Verification Processing Time from Days to Hours
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Jun 9, 2005
Synopsys' Galaxy Design Platform Provides Advanced Power Closure and Enhanced Yield Capabilities for Reference Flow 6.0
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Jun 8, 2005
Synopsys to Deliver Complete System to Implementation Solution for Power Architecture Designs
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Jun 7, 2005
IC Compiler Delivers 10 Percent Higher Speed With Faster Time-To-Results
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Jun 7, 2005
Synopsys' PSM, Hercules PVS, Proteus OPC and TCAD Offer FastDFM Flow Turnaround Time
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Jun 6, 2005
DesignWare Digital Controller Cores and PHY IP Available Today for the PCI Express 1.1 Standard
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Jun 6, 2005
Proven SATA Verification IP Lowers Risk and Speeds Verification for SoC Designers
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May 31, 2005
Latest Version of the VCS® Solution Speeds Standards-Based Verification by Unifying SystemVerilog and SystemC™ Languages in a Single Tool
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May 31, 2005
VCS® Native Testbench Technology and Comprehensive Coverage Enable Huawei to Achieve First-Silicon Success in Less Time
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May 25, 2005
Synopsys DesignWare® PHY IP Enables Reliable USB Connectivity for IBM and Chartered Foundry Customers
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May 25, 2005
Complete RTL to Production-Ready GDSII Flow Speeds 90-nm Designs
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May 24, 2005
i-Virtual Stepper System Integrates Lithography Simulation and Automation to Deliver Improved Mask Turn-Around Time and Yield
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May 23, 2005
Design Compiler® 2005 Delivers Accurate Correlation to Post-Layout Timing for RTL Designers