Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Sep 28, 2006
More Than 400 Engineers Gather at Eighth Annual Regional User's Conference
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Sep 27, 2006
Second Consecutive Runtime Improvement for TetraMAX Tool Offers Designers Substantial Productivity Benefits
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Sep 25, 2006
High-Performance Sitka Evaluation and Development Platform Allows Designers to Test and Debug Applications Using the DesignWare PCI Express IP in Hardware
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Sep 20, 2006
Solutions Target Improved Lithography Modeling Accuracy, Reduced Time-to-Silicon, and Improved Manufacturing Yield
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Sep 19, 2006
Technology Proven to Help Customers Achieve Ultra Low Power IC Designs
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Sep 19, 2006
PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
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Sep 15, 2006
Synopsys Dedicates Scan Chain Inventions to Public Domain
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Sep 13, 2006
Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups
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Sep 5, 2006
High-Performance DesignWare IP for USB, PCIe, SATA and XAUI Now Available
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Aug 28, 2006
Concurrent Multi-Mode Optimization Speeds Timing Closure
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Aug 21, 2006
Topographical Technology Improves Designer Efficiency and Reduces Turnaround Time
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Aug 16, 2006
Acquisition Will Enable Tighter Integration With DFM and Manufacturing Tools to Optimize Yield and Increase Predictability
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Aug 2, 2006
Variation-based Models Built on Proven Composite Current Source Technology to Deliver Improved Accuracy
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Jul 27, 2006
VhdlCohen Publishes A Pragmatic Approach to VMM Adoption: 'A SystemVerilog Framework for Testbenches'
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Jul 26, 2006
EDA Company Honored for Key Contributions to Open Source Parser for Liberty™ Library Format
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Jul 26, 2006
Checkers Proven to Accelerate Customer Adoption of SystemVerilog Assertions to Benefit Entire Industry
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Jul 25, 2006
Scalable DFM Checks Accelerate Time-to-Yield for Designers
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Jul 24, 2006
Toshiba to Deploy Integrated, Production-Proven DFM Technology into Standard Layout Flow
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Jul 24, 2006
Built on Gold Standards, PrimeTime VX and Star-RCXT VX Tools Deliver Foundation for Comprehensive Variation-aware Design Solution for Sub-65nm Design
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Jul 24, 2006
Integration of Production-Proven Design and Manufacturing Technology Accelerates Time to Yield
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Jul 20, 2006
More Than 50 Tapeouts Prove DFT MAX Reduces Test Time and Cost
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Jul 19, 2006
Multiple Multi-Voltage Tapeouts Completed With Galaxy Advanced Low-Power Solution
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Jul 19, 2006
Common Platform Technology Reference Flow Adds Critical Area Design-for-Manufacturing Capability in IC Compiler
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Jul 18, 2006
Reference Flow 7.0 Incorporates Latest Technologies for Low Power and Yield Optimization to Address 65-nanometer Design Challenges
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Jul 18, 2006
Users Embrace the VMM Methodology for SystemVerilog and Synopsys' VCS® Native Testbench
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Jul 13, 2006
Founding Technical Advisory Board Members to Hold Inaugural Meeting at Design Automation Conference in San Francisco
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Jul 12, 2006
Synopsys Expands DesignWare Library With More Than 20 New IP Components
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Jul 11, 2006
Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes
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Jul 5, 2006
VCS Native Testbench (NTB) and the Verification Methodology Manual (VMM) for SystemVerilog Help Accelerate Aggressive Verification Schedule
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Jun 29, 2006
Sunplus Selects Synopsys Professional Services to Achieve Aggressive Schedule and Cost Goals
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Jun 28, 2006
Silicon-Proven DesignWare PHY Cuts Power and Size in Half for Portable, High-Volume Consumer SoCs
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Jun 28, 2006
NanoTime Extends Synopsys' Leadership in Transistor-Level Simulation and Analysis
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Jun 27, 2006
IC Compiler Reduces Chip Cost by Achieving Over 90% Area Utilization
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Jun 26, 2006
Release Brings New Advances in Yield, Low Power, and Testability
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Jun 13, 2006
Sentaurus TCAD Accelerates Advanced Technology Development With New Process and Device Modeling Capabilities
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Jun 13, 2006
Synopsys' Galaxy™ Design and Discovery™ Verification Platforms and DesignWare® IP to Accelerate SoC Development
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Jun 7, 2006
Bridge Delivers High-Throughput Connection to Multiple PCI Express Technology-Based Systems and Peripherals
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May 25, 2006
Automated Prototyping Flow Delivers Predictable Time-to-Tapeout
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