Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Mar 30, 2020Latest Photonic Solutions Portfolio Accelerates Design of AR/VR Systems, Optical Communications, and PICs
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Mar 27, 2020Co-CEO to Provide Brief Commentary on COVID-19 Situation
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Mar 26, 2020Silicon-Proven DesignWare IP for PCI Express 5.0 and DDR4 Delivers Low Latency and High Bandwidth for Data-Intensive Workloads
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Mar 25, 2020Latest Agreement Builds on SiFive's Successful Use of Synopsys Solutions
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Mar 24, 2020Version 9.0, Now Available, Brings Improved Polarization Modeling, Expanded Stray Light Analysis, and Optimization of Curved Display Systems
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Mar 23, 2020New Native System Verilog Ethernet VIP Complements Synopsys' 112G High-Speed SerDes PHY IP to Enable High-Performance Cloud Computing Solutions
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Mar 19, 2020DesignWare 56G PHY Delivers Leading Power and Performance with High Reliability
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Mar 16, 2020Unique RTL Tuning Environment Reduces Physical Design Iterations
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Mar 11, 2020Introducing Synopsys DSO.ai™: The world's first autonomous AI application for chip design
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Mar 11, 2020New Machine Learning-Based Simpleware ScanIP Option Provides 20-50 Times Speedup and Precisely Automates Previously Manual Segmentation for Medical Device Design and Pre-Surgical Planning
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Mar 10, 2020Alphawave Adopts Synopsys Solution to Accelerate Design of High-speed Connectivity IP
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Mar 4, 2020Recent Advances in Machine Learning (ML) Technologies Extend Synopsys' QoR Leadership
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Feb 27, 2020Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise
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Feb 25, 2020DesignWare HBM2E PHY IP in TSMC's N7 Process Delivers High Throughput for Advanced Graphics, High-Performance Computing and Networking SoCs
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Feb 19, 2020Q1 2020 Financial Highlights
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Feb 19, 2020Synopsys and AMD Collaborate to Optimize Synopsys' Fusion Compiler for Servers Powered by AMD EPYC Processors
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Feb 13, 2020Integrated Hardware and Software IP Subsystem Delivers Efficient 3GPP Release 14-Compliant Communications for Machine to Machine, Smart Cities, and Industrial Automation Applications
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Feb 12, 2020New Polaris capabilities combine SCA and SAST in the IDE, enabling developers to proactively find and fix security risks across third-party and custom components
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Jan 23, 2020Silicon-based Hardware Platform with DSP Functionality Accelerates Software Development for Mobile Baseband, Voice/Speech, Home Audio, and Artificial Intelligence Applications
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Jan 22, 2020Synopsys Provides Validation Services for Applications Deployed on Finastra's FusionFabric.cloud Open Innovation Platform
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Jan 16, 2020Consortium Brings Together Leading Automotive and Technology Industry Companies to Accelerate Deployment of Self-Driving Vehicles
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Jan 9, 2020Virtualizer Development Kit Deployed at NXP, Tier 1, OEMs, and Software Ecosystem Vendors 18 Months Before Silicon Availability
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Jan 7, 2020Acquisition Broadens DesignWare IP Portfolio and Adds a Team of Experienced R&D Engineers to Accelerate Physical IP Development
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Jan 7, 2020New Low-Power Codec Optimized for Synopsys' ARC Processor IP Enables High-Quality Audio and Voice Streaming from Smart Home, Mobile, and Wearable Devices
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Dec 20, 2019Enables Hardware and Software Teams to Optimize Software Performance Within Four Weeks
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Dec 19, 2019A Holistic Solution Catalyzing Sustainable Gains in Engineering Quality, Speed, and Efficiency for Integrated Automotive Systems
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Dec 17, 2019Synopsys Introduces New CODE V Release with Enhanced Optomechanical Product Design and VisualizationCODE V Version 11.3 Extends Optical Engineering Leadership with New Features for CAD Modeling, Freeform Optics Design, and Project Management
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Dec 12, 2019ISO 26262 ASIL Compliant ARC EM Processor IP Enables Calterah to Accelerate Safety Certification for Next-Generation Millimeter Wave Radar Chip
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Dec 4, 2019Q4 2019 Financial Highlights
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Nov 18, 2019Samsung Releases 5LPE AMS Reference Flow Based on Synopsys Custom Design Platform
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Nov 15, 2019
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Nov 12, 2019Always-On Sensing ASIC Enables Machine Learning for Ultra-Low Power Applications
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Nov 11, 2019Part of a Broader Collaboration for Functional Safety and Manufacturing Test to Achieve ASIL-D Level Design Safety
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Nov 11, 2019Acquisition Will Expand DesignWare IP Portfolio and Add a Team of Experienced R&D Engineers to Serve Growing AI and Cloud Markets
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Nov 7, 2019Signoff Abstract Model Flow for Hierarchical Verification Delivers Higher Performance and Capacity with No Loss in Quality of Results or Debug Visibility
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Oct 30, 2019New Agreement Includes Optimization of ZeBu and VCS Software for AMD EPYC Processor-based Servers
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Oct 29, 2019DesignWare Die-to-Die PHY Enables Ultra- and Extra-Short Reach Connectivity in Large, Multi-Chip Module Designs
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Oct 29, 2019HAPS-80's High Performance and Cost Effectiveness Has Driven Adoption by More Than 100 Companies
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Oct 28, 2019Silicon-Proven DesignWare Interface and Foundation IP Portfolios Lower Integration Risk and Accelerate Time to Market for Automotive Application
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Oct 23, 2019Astera Labs Delivers Industry's First Commercially Available PCIe 5.0 Retimer SoC
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