Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Aug 6, 2020Study conducted by analyst firm ESG explores security trends and challenges emerging in modern application development
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Aug 3, 2020Brings Valuable Combination of Technical, Product Development and Go-To-Market Expertise
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Jul 20, 2020VCS Delivers Highest Verification Throughput for a 50 Billion+ Transistor Design
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Jul 15, 2020High-Quality DesignWare Interface and Processor IP for Efficient Real-Time Connectivity and Machine Learning Processing Accelerate Design Schedule and Lower Risk
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Jul 14, 2020Synopsys Announces Industry's First JEDEC DDR5 Verification IP for Next-Generation DRAM/DIMM DesignsNative SystemVerilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis
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Jul 7, 2020Silicon-Proven DesignWare IP Delivers Unmatched Performance, Power, and Area
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Jun 29, 2020Multi-year Agreement Accelerates Design and Verification of Arm-based SoCs
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Jun 26, 2020
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Jun 25, 2020Advances SoC Design by Integrating Scalable Hardware Security Mechanisms Leveraging Academic and Commercial Partner Expertise, and Synopsys' Industry-Leading EDA Platforms and IP
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Jun 23, 2020Company Achieves Carbon Neutrality Certification for the Second Consecutive Year
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Jun 17, 2020Cloud-scalable Synopsys Fusion Design, Custom Design, and Verification Continuum products available through the platform
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Jun 15, 2020Major reduction in turnaround time for next-generation chips achieved through collaboration
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Jun 10, 2020Customers benefit from increased silicon data analysis to improve design implementation, product yield ramp and manufacturing test efficiency
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Jun 10, 2020LucidShape CAA V5 Based v2020.06 offers powerful design features and stunning photorealistic rendering capabilities for headlight, tail light, and signal light innovations
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Jun 4, 2020High-Quality DesignWare Security IP Protects Against Security Threats for Connected Devices
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Jun 3, 2020Successful Tapeout of the DesignWare USB4 PHY Test Chip on 5nm Process Reduces Risk and Accelerates Time-to-Market for SoCs Supporting the 40 Gbps USB Specification
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Jun 1, 2020More than 100 customers have adopted Design Compiler NXT since its introduction one year ago
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Jun 1, 2020Synopsys Solutions Deliver Multi-gigahertz Performance with Lowest Power and Area for Baikal-M1000 Processor Designs
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May 28, 2020DesignWare DDR IP Delivers High Performance Memory Interface for Compute-Intensive Artificial Intelligence Applications in Multiple Silicon Processes Including 7-nm
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May 26, 2020Synopsys Design and Verification Platforms and DesignWare Interface IP Enable Optimized Power, Performance and Area and Faster Time to Market
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May 22, 2020Synopsys solution deployed at Panasonic for all analog, mixed-signal & RF designs
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May 21, 2020Accelerated Software Development by More Than Two Months
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May 20, 2020Q2 2020 Financial Highlights
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May 18, 2020Strategic collaboration with TSMC delivers additional gains in performance and ultra-low power, and accelerates the path to next-generation designs
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May 12, 2020Analysis of more than 1,250 commercial codebases finds that open source security, license compliance, and operational risk remains widespread
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May 11, 2020High-Quality DesignWare Interface and Foundation IP Deliver Leading Power, Performance and Area
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May 1, 2020Synopsys Placed in Highest and Furthest Overall Position for its Ability to Execute and Completeness of Vision Two Years in a Row
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Apr 28, 2020Unique platform delivers automation and visualization for 2.5D/3D package design and implementation, with power, thermal, and noise-aware optimization
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Apr 23, 2020Content, now available, includes video from Synopsys co-CEO Aart de Geus discussing SNUG and new product introductions
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Apr 13, 2020ZeBu's Performance Enabled First Silicon Success of Tensor Streaming Processor Architecture
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Apr 7, 2020DesignWare ARC HS6x Processors Based on New 32/64-bit ARCv3 Instruction Set Architecture Extend Addressable Memory, Scale Up To 12 Cores
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Apr 6, 2020Synopsys' Prototyping Solutions Enable Faraday Customers to Accelerate Time-to-Market with Concurrent Hardware and Software Development
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Apr 2, 2020Broad Deployment of Synopsys' Fusion Design Platform Accelerating Delivery of Market-shaping Solutions
Mar 31, 2020DesignWare PHY and Controllers Operate at Up to 24 Gb/s for High-Performance Imaging and Automotive SoCs-
Mar 30, 2020Latest Photonic Solutions Portfolio Accelerates Design of AR/VR Systems, Optical Communications, and PICs
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Mar 27, 2020Co-CEO to Provide Brief Commentary on COVID-19 Situation
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Mar 26, 2020Silicon-Proven DesignWare IP for PCI Express 5.0 and DDR4 Delivers Low Latency and High Bandwidth for Data-Intensive Workloads
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Mar 25, 2020Latest Agreement Builds on SiFive's Successful Use of Synopsys Solutions
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Mar 24, 2020Version 9.0, Now Available, Brings Improved Polarization Modeling, Expanded Stray Light Analysis, and Optimization of Curved Display Systems
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Mar 23, 2020New Native System Verilog Ethernet VIP Complements Synopsys' 112G High-Speed SerDes PHY IP to Enable High-Performance Cloud Computing Solutions
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Mar 19, 2020DesignWare 56G PHY Delivers Leading Power and Performance with High Reliability
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Mar 16, 2020Unique RTL Tuning Environment Reduces Physical Design Iterations
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Mar 11, 2020Introducing Synopsys DSO.ai™: The world's first autonomous AI application for chip design
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Mar 11, 2020New Machine Learning-Based Simpleware ScanIP Option Provides 20-50 Times Speedup and Precisely Automates Previously Manual Segmentation for Medical Device Design and Pre-Surgical Planning
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Mar 10, 2020Alphawave Adopts Synopsys Solution to Accelerate Design of High-speed Connectivity IP
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Mar 4, 2020Recent Advances in Machine Learning (ML) Technologies Extend Synopsys' QoR Leadership
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Feb 27, 2020Delivers 3X Higher Performance, Multi-Billion Gate Capacity, and 10X Lower Noise
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Feb 25, 2020DesignWare HBM2E PHY IP in TSMC's N7 Process Delivers High Throughput for Advanced Graphics, High-Performance Computing and Networking SoCs
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Feb 19, 2020Q1 2020 Financial Highlights
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Feb 19, 2020Synopsys and AMD Collaborate to Optimize Synopsys' Fusion Compiler for Servers Powered by AMD EPYC Processors
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Feb 13, 2020Integrated Hardware and Software IP Subsystem Delivers Efficient 3GPP Release 14-Compliant Communications for Machine to Machine, Smart Cities, and Industrial Automation Applications
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Feb 12, 2020New Polaris capabilities combine SCA and SAST in the IDE, enabling developers to proactively find and fix security risks across third-party and custom components
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Jan 23, 2020Silicon-based Hardware Platform with DSP Functionality Accelerates Software Development for Mobile Baseband, Voice/Speech, Home Audio, and Artificial Intelligence Applications
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Jan 22, 2020Synopsys Provides Validation Services for Applications Deployed on Finastra's FusionFabric.cloud Open Innovation Platform
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Jan 16, 2020Consortium Brings Together Leading Automotive and Technology Industry Companies to Accelerate Deployment of Self-Driving Vehicles
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Jan 9, 2020Virtualizer Development Kit Deployed at NXP, Tier 1, OEMs, and Software Ecosystem Vendors 18 Months Before Silicon Availability
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Jan 7, 2020Acquisition Broadens DesignWare IP Portfolio and Adds a Team of Experienced R&D Engineers to Accelerate Physical IP Development
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Jan 7, 2020New Low-Power Codec Optimized for Synopsys' ARC Processor IP Enables High-Quality Audio and Voice Streaming from Smart Home, Mobile, and Wearable Devices
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Dec 20, 2019Enables Hardware and Software Teams to Optimize Software Performance Within Four Weeks
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Dec 19, 2019A Holistic Solution Catalyzing Sustainable Gains in Engineering Quality, Speed, and Efficiency for Integrated Automotive Systems
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Dec 17, 2019Synopsys Introduces New CODE V Release with Enhanced Optomechanical Product Design and VisualizationCODE V Version 11.3 Extends Optical Engineering Leadership with New Features for CAD Modeling, Freeform Optics Design, and Project Management
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Dec 12, 2019ISO 26262 ASIL Compliant ARC EM Processor IP Enables Calterah to Accelerate Safety Certification for Next-Generation Millimeter Wave Radar Chip
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Dec 4, 2019Q4 2019 Financial Highlights
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Nov 18, 2019Samsung Releases 5LPE AMS Reference Flow Based on Synopsys Custom Design Platform
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Nov 15, 2019
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Nov 12, 2019Always-On Sensing ASIC Enables Machine Learning for Ultra-Low Power Applications
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Nov 11, 2019Part of a Broader Collaboration for Functional Safety and Manufacturing Test to Achieve ASIL-D Level Design Safety
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Nov 11, 2019Acquisition Will Expand DesignWare IP Portfolio and Add a Team of Experienced R&D Engineers to Serve Growing AI and Cloud Markets
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Nov 7, 2019Signoff Abstract Model Flow for Hierarchical Verification Delivers Higher Performance and Capacity with No Loss in Quality of Results or Debug Visibility
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Oct 30, 2019New Agreement Includes Optimization of ZeBu and VCS Software for AMD EPYC Processor-based Servers
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Oct 29, 2019DesignWare Die-to-Die PHY Enables Ultra- and Extra-Short Reach Connectivity in Large, Multi-Chip Module Designs
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Oct 29, 2019HAPS-80's High Performance and Cost Effectiveness Has Driven Adoption by More Than 100 Companies
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Oct 28, 2019Silicon-Proven DesignWare Interface and Foundation IP Portfolios Lower Integration Risk and Accelerate Time to Market for Automotive Application
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Oct 23, 2019Astera Labs Delivers Industry's First Commercially Available PCIe 5.0 Retimer SoC
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Oct 22, 2019DesignWare ARC VPX5 and VPX5FS DSP Processors Incorporate Ultra-wide Vector Architecture to Accelerate Highly Parallel Automotive, Sensor Fusion, and Communications Applications
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Oct 17, 2019Synopsys and Samsung Foundry Collaboration Delivers Customized Solution to Support 5G, AI, and HPC Applications
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Oct 7, 2019Certified Tools and Reference Flow Enable Early Adopters' Implementation of Advanced Arm Core
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Oct 7, 2019VC Functional Safety Manager Reduces ISO 26262 FMEA/FMEDA and Fault Classification Effort by Up to 50 Percent
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