Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Sep 24, 2020DesignWare IP Delivers Significant Performance and Power Advantages for Cloud Computing and Edge AI SoCs on GF 12LP+ Solution
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Sep 16, 2020ASIP Designer Tool Provides Rapid Architectural Exploration and Automatic Generation of Software Development Kits to Accelerate Design Time
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Sep 15, 2020The 11th iteration of the Building Security In Maturity Model reflects how organizations are adapting their software security efforts to support modern software development paradigms
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Sep 10, 2020Integration of DSP-Enhanced ARC Processor Enables Deployment of Advanced Sound Processing Features in Next-Generation Headsets
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Sep 9, 2020Synopsys OptoCompiler Enables Fast, Easy and Scalable Photonic IC Development
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Sep 3, 2020Combination of Synopsys' ARC IoT Communications IP Subsystem with Nestwave's Geolocation IP Eliminates the Need for a Dedicated Positioning Chipset
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Sep 1, 2020Elektrobit is the First Automotive Software Company to Collaborate with Synopsys on Providing Software for Synopsys ARC Functional Safety Processors Used in Automotive ECUs
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Aug 27, 2020Silicon-Proven 56G Ethernet PHY Delivers True Long Reach Performance with Flexible Data Rates and Low Latency
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Aug 25, 2020Attendees Can Explore Processor IP Solutions that Accelerate SoC Development for Automotive, Artificial Intelligence, IoT and High-Performance Embedded Applications
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Aug 25, 2020Synopsys 3DIC Compiler platform reduces design turnaround time for chip-package co-design implementation
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Aug 25, 2020Certified Synopsys design solutions enable HPC, mobile, 5G, and AI SoCs and offer cutting-edge power savings and performance
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Aug 20, 2020IC Validator delivers 40 percent lower cost of ownership with optimal utilization of cloud
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Aug 19, 2020NSITEXE Accelerates Customer Engagements Using High-Performance HAPS Solution
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Aug 19, 2020Deep Technical and Business Expertise Ideal for Synopsys' Next Wave of Innovation, Growth and Profitability
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Aug 19, 2020Q3 2020 Financial Highlights
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Aug 12, 2020Multi-Discipline Solution Enables Earlier, More Productive and Scalable Development Across Power Electronics to Software Development and Test
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Aug 6, 2020Study conducted by analyst firm ESG explores security trends and challenges emerging in modern application development
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Aug 3, 2020Brings Valuable Combination of Technical, Product Development and Go-To-Market Expertise
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Jul 20, 2020VCS Delivers Highest Verification Throughput for a 50 Billion+ Transistor Design
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Jul 15, 2020High-Quality DesignWare Interface and Processor IP for Efficient Real-Time Connectivity and Machine Learning Processing Accelerate Design Schedule and Lower Risk
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Jul 14, 2020Synopsys Announces Industry's First JEDEC DDR5 Verification IP for Next-Generation DRAM/DIMM DesignsNative SystemVerilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis
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Jul 7, 2020Silicon-Proven DesignWare IP Delivers Unmatched Performance, Power, and Area
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Jun 29, 2020Multi-year Agreement Accelerates Design and Verification of Arm-based SoCs
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Jun 26, 2020
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Jun 25, 2020Advances SoC Design by Integrating Scalable Hardware Security Mechanisms Leveraging Academic and Commercial Partner Expertise, and Synopsys' Industry-Leading EDA Platforms and IP
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Jun 23, 2020Company Achieves Carbon Neutrality Certification for the Second Consecutive Year
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Jun 17, 2020Cloud-scalable Synopsys Fusion Design, Custom Design, and Verification Continuum products available through the platform
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Jun 15, 2020Major reduction in turnaround time for next-generation chips achieved through collaboration
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Jun 10, 2020Customers benefit from increased silicon data analysis to improve design implementation, product yield ramp and manufacturing test efficiency
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Jun 10, 2020LucidShape CAA V5 Based v2020.06 offers powerful design features and stunning photorealistic rendering capabilities for headlight, tail light, and signal light innovations
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Jun 4, 2020High-Quality DesignWare Security IP Protects Against Security Threats for Connected Devices
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Jun 3, 2020Successful Tapeout of the DesignWare USB4 PHY Test Chip on 5nm Process Reduces Risk and Accelerates Time-to-Market for SoCs Supporting the 40 Gbps USB Specification
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Jun 1, 2020More than 100 customers have adopted Design Compiler NXT since its introduction one year ago
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Jun 1, 2020Synopsys Solutions Deliver Multi-gigahertz Performance with Lowest Power and Area for Baikal-M1000 Processor Designs
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May 28, 2020DesignWare DDR IP Delivers High Performance Memory Interface for Compute-Intensive Artificial Intelligence Applications in Multiple Silicon Processes Including 7-nm
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May 26, 2020Synopsys Design and Verification Platforms and DesignWare Interface IP Enable Optimized Power, Performance and Area and Faster Time to Market
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May 22, 2020Synopsys solution deployed at Panasonic for all analog, mixed-signal & RF designs
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May 21, 2020Accelerated Software Development by More Than Two Months
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May 20, 2020Q2 2020 Financial Highlights
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May 18, 2020Strategic collaboration with TSMC delivers additional gains in performance and ultra-low power, and accelerates the path to next-generation designs
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May 12, 2020Analysis of more than 1,250 commercial codebases finds that open source security, license compliance, and operational risk remains widespread
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May 11, 2020High-Quality DesignWare Interface and Foundation IP Deliver Leading Power, Performance and Area
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