Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
-
-
Nov 1, 2017
Successful Testing of DesignWare Cryptography Software Library Enables Development of Highly Secure IoT Systems
-
Oct 31, 2017
Enhanced BIST and Repair Algorithms for 7-nm FinFET Processes Increase Memory IP Test Coverage and Accelerate Power-On Initialization
-
Oct 31, 2017
Company Standardizes on TetraMAX II Solution to Create Manufacturing Tests for All Designs
-
Oct 31, 2017
Report highlights progress over past decade, identifying key indicators of project maturity and underscoring the importance of measuring risk
-
Oct 30, 2017
ASIL D Ready Certified DesignWare Embedded Test and Repair IP Speeds Functional Safety Qualification for Automotive ADAS Applications
-
Oct 30, 2017
Provides Highest Degree of Safety Related Confidence and Accelerates Functional Safety Qualification
-
Oct 26, 2017
Recognition for Leadership in the Optics Industry and The Optical Society
-
Oct 25, 2017
Program's Goal is to Advance Superconductor Design and Propel Electronics Beyond CMOS
-
Oct 23, 2017
Comprehensive Synopsys Platform Enables Accelerated Verification of High-Performance, Low-Power RISC-V Processors and SoCs
-
Oct 18, 2017
New Virtualizer Design Kits Enable Automotive Tier 1 and OEM Companies to Start Software Development, Integration and Test Before Silicon
-
Oct 17, 2017
Acquisition Adds One-Time Programmable Non-Volatile Memory IP to DesignWare NVM IP Offering
-
Oct 9, 2017
Release 2017.09 of the RSoft Product Family Now Available
-
-
Oct 5, 2017
Native SystemVerilog USB VIP Features Built-in Coverage, Verification Plan, Protocol-Aware Debug and Source Code Test Suites
-
-
Sep 24, 2017
Reference Flow for Silicon-Proven Design Platform Accelerates Path to Lower Power and Design Cost
-
Sep 20, 2017
DesignWare Interface and Analog IP Enables Faster Time-to-Volume for Energy-Efficient IoT and Mobile SoCs
-
Sep 20, 2017
Certification Enables Optimized Implementation and Predictable Signoff
-
Sep 20, 2017
Latest Iteration of the Building Security in Maturity Model Shows More Organizations Jumpstarting their Software Security Initiatives with Assessments and Improving Over Time
-
-
Sep 19, 2017
DesignWare ARC Secure IP Subsystem Provides Programmable Hardware Root of Trust to Protect Against Malware, Tampering and Exploitation of Communication Protocols in SoCs
-
Sep 19, 2017
Comprehensive Foundry Reference Flow Leverages Industry-leading IC Compiler II
-
Sep 18, 2017
Materials Modeling Enables Semiconductor Manufacturers to Save Time and Cost for Advanced Process Node Development
-
Sep 18, 2017
Platform Consisting of ARC Data Fusion IP Subsystem, Peripherals, Operating System and Software Development Tools Enables Immediate Productivity
-
Sep 18, 2017
IoT Platform Accelerates Designs for IoT Edge Devices with Synopsys Silicon-Proven ARC Data Fusion IP Subsystem, Brite ASIC Design Services and SMIC 55-nm Ultra-Low Power Process
-
Sep 18, 2017
TSMC Awards recognize Synopsys' Collaboration on Interface IP, Joint Development of 7nm FinFET Plus and 12FFC Design Infrastructures and Joint Delivery of an Automotive Design Enablement Platform
-
-
Sep 13, 2017
Combination of Alango's Far-Field Voice Enhancement Software Technologies and Synopsys' ARC IP Subsystem Provides Ideal Low-Power Solution for Voice-Controlled Devices
-
Sep 12, 2017
Logic Libraries and Embedded Memories for TSMC 40LP and 40ULP eFlash Processes Improve Energy Efficiency for IoT Devices
-
-
Sep 11, 2017
DesignWare Foundation and Interface IP on TSMC 7-nm Process Technology Enables Faster Time-to-Market for Mobile, Automotive and High-Performance Computing SoCs
-
Sep 11, 2017
Platform-Wide Certification for TSMC's Latest Advanced-Process Technology
-
Sep 11, 2017
Platform-Wide Enhancements Across Digital and Custom Design Tools Deliver a Production-Ready Flow
-
Sep 8, 2017
Updating GAAP targets; No Change to Non-GAAP targets
-
Sep 6, 2017
ARC Processor Summit Attendees Will Learn about Solutions to Address Design Challenges in IoT Security, Automotive Safety and Embedded Vision Applications
-
Sep 5, 2017
Latest Release Offers Enhanced MTF Optimization and Visualization of Compact Optical Devices
-
Sep 5, 2017
Comprehensive Synopsys Platform Enables Accelerated Verification of High-Performance, Low-Power CPU, GPU and System IP for Mobile SoCs
-
-
Aug 29, 2017
New Bluetooth Low Energy PHY Delivers Up to 60 percent Smaller Area for Low-Power IoT Designs
-
Aug 24, 2017
In addition, 41 Percent Believe Lack of Skilled Security Personnel or Training is Key Secondary Challenge
-
Aug 16, 2017
Q3 2017 Financial Highlights
-
Aug 9, 2017
Analysis of 4.8 Billion Fuzz Tests Identified 6.6 Seconds as the Average Time to First Failure for the Least Mature Protocol
-
Aug 8, 2017
CNN-based Image Classification Software with DesignWare EV6x Vision Processor IP Delivers High Recognition Rate with Small Memory Footprint for Power-Constrained Devices
-
Aug 8, 2017
18th Annual Competition Recognizes Student Achievements in Optical Design
-
-
Aug 1, 2017
DesignWare PHY IP for LPDDR4, MIPI, PCI Express and Ethernet Delivers High Reliability for ADAS and Autonomous Vehicle SoCs
-
Jul 26, 2017
HAPS-80 Delivers 2X Performance and 2X Capacity Compared to Prior Generation
-
Jul 25, 2017
New DesignWare HBM2 Controller, PHY and Verification IP Enables High-Bandwidth, Power-Efficient Systems
-
Jul 13, 2017
Latest Product Updates Expand Coverage for New Programming Languages and MISRA Compliance, Improve Integration Capabilities and Increase Flexibility
-
Jun 29, 2017
Industry Experts Explore DevOps Security, IoT Security across Verticals and How to Build Security into the Software Development Lifecycle
-
Jun 28, 2017
VC Formal Delivers Faster Convergence for Complex Multi-Functional Product Designs
-
Jun 26, 2017
Enhanced DesignWare EV6x Family Delivers Up to 4.5 TeraMACs/sec for Real-Time Vision Processing
-
Jun 20, 2017
Enablement Includes Industry-Leading IC Compiler II P&R Solution and DesignWare Embedded Memory IP
-
-
Jun 19, 2017
Exclusive Product Integration To Combine Power And Reliability Signoff Solution With Physical Implementation Solution For In-Design Analysis To Spur Future Smart Product Development
-
-
Jun 15, 2017
Next-generation Formal Verification Technology Uniquely Positioned for Performance and Capacity Required for Complex SoCs
-
Jun 14, 2017
World's Leading Solution Provider of Video Surveillance[1] Deploys Synopsys Solutions to Build Security and Quality into Its Software Development Lifecycle and Supply Chain
-
Jun 8, 2017
Online Access to Comprehensive Suite of Free and Open Source Software and Tools Provides One-Stop Shop for Software Developers Programming ARC Processor-based Devices
-
-
-
Jun 6, 2017
New DesignWare CCIX Controller, PHY and Verification IP Supports Speeds Up to 25Gbps and Enables Faster Data Access
-
Jun 6, 2017
Analysis of More Than 120,000 Applications Found that Half of Third-Party Software Components in Use Are Outdated
-
Jun 5, 2017
Solution enables secure, remote lifecycle management for automotive, IoT and mobile applications
-
Jun 5, 2017
Demonstration Proves Successful System Bring-Up and 16 GT/s Data Transfer of the DesignWare IP for PCI Express 4.0 Specification Targeting High-Performance Cloud Computing Designs
-
-
-
May 31, 2017
Complete Compliant MIPI Display Solution Reduces Data Transmission Bandwidth for Mobile, Virtual Reality and Automotive SoCs
-
May 30, 2017
ZeBu Server Enables Hardware and Software Teams to Work in Parallel, Saving Months on Schedules
-
May 28, 2017
New Optimized QuickStart Implementation Kits To Help Designers Quickly Achieve Target QoR Using Synopsys Design Platform
-
-
May 25, 2017
Survey of Medical Device Manufacturers and Healthcare Delivery Organizations Reveals Industry's Lack of Confidence and Alignment in Securing Medical Devices
-
May 24, 2017
Synopsys Design Platform is Ready for Early Engagement with Mutual Customers
-
May 24, 2017
Silicon-Proven IP Portfolio Provides Low-Risk Path to Silicon Success for SoC Designs on Samsung's Advanced Process Technologies
-
May 24, 2017
IC Validator delivers physical signoff in hours with massively parallel architecture
-
May 24, 2017
Synopsys Custom Design Platform Certified for IoT, Mobile Computing and Automotive Applications
-
May 23, 2017
DesignWare ARC HS4x Family Delivers Twice the Signal Processing Performance of Previous ARC HS Cores with Integrated DSP Capability
-
May 22, 2017
DesignWare PHY IP Cuts Power and Area by More Than 35 Percent for High-Performance Computing Applications Including Machine Learning and Artificial Intelligence
-
-
May 18, 2017
Solution Supports USB, USB PD and DisplayPort on Type-C and is Expandable to Future Protocols
-
-
-
May 11, 2017
Massively Parallel Architecture Accelerates Physical Signoff and Delivers Industry-Leading Turnaround Time
-
May 10, 2017
Delivers Accuracy Within 5% of Power Signoff
-
-
May 4, 2017
Delivers Higher Performance and Comprehensive Variation Analysis for Robust AMS Design
-
May 4, 2017
Seamless Integration of Synopsys’ Synplify Pro and Identify RTL Debugger With Microsemi’s Libero SoC Design Suite for FPGA Customers
-
-
May 3, 2017
Combination of InfoSec Global Agile Cryptography with Synopsys tRoot Hardware Secure Module Increases Security for Industrial IoT Designs
-
May 2, 2017
Combination of jNet ThingX JavaCard OS with Synopsys' Anti-Tamper ARC SEM Cores Eases Development of Common Criteria Certified SoCs
-
Apr 27, 2017
New Version of LucidDrive Supports Analysis of Headlight Road Performance in Dynamic Traffic Situations
-
Apr 27, 2017
DesignWare True Random Number Generators, Logic Libraries, Embedded Memories and STAR Memory System Provide Low-Risk Path to First-Pass Silicon Success
-
Apr 26, 2017
Seamless Integration of Industry's Fastest Emulation System into Dataflow Processing Unit Development Effort
-
Apr 25, 2017
ASIL B and D Ready DesignWare IP Accelerates Functional Safety Assessments for Automotive SoCs
-
Apr 20, 2017
DesignWare IP Subsystem Integrates New Audio/Voice/Speech and I3C Hardware and Software to Address Expanding Processing Requirements of Secure, Multi-Sensor SoCs
-
Apr 12, 2017
Native SystemVerilog VIP Includes Built-In Coverage, Verification Planning, and Protocol-Aware Debug
-
Mar 28, 2017
Industry leaders in CPU, GPU and fabless SoC markets adopt IC Validator's massively parallel distributed processing for overnight signoff
-
Mar 27, 2017
Updated Interface with Synopsys Sentaurus TCAD Products and New High-Speed Optical Absorption Calculation Now Available
-
Mar 21, 2017
Bitcoin-mining Design-based Kit Features Complete RTL-to-GDSII Low Power Methodology