Press Releases
Press Releases are listed below in chronological order with the most recent one appearing first. Please use the tool below to search for press releases in a particular year, category or that contain a keyword. For additional search options, please use the Advanced Search tool.
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Nov 21, 2006Builds Electronic Design Automation Industry's First Supercomputer to Claim 242nd Spot on Top500 List
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Nov 21, 2006Simple Implementation and Predictable Results Were Key Drivers in Selection
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Nov 20, 2006Combination of Design and Verification Platforms With DesignWare® IP Meets Tight Area, Power and Performance Goals
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Nov 20, 2006Freescale Deploys VCS Native Testbench for SystemVerilog-Based Verification
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Nov 7, 2006IC Compiler Enables 10 Percent Die-Size Shrink and 2X Faster Turnaround Time
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Oct 31, 2006San Jose Mercury News High-Tech Journalist to Present Keynote
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Oct 30, 2006Complete Solution Will Include Memory Controller and Mixed-Signal PHY to Reduce Risk and Speed System Integration
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Oct 25, 2006Bridge Connects a Wealth of PCI Express Technology-Based Systems and Peripherals to AMBA 2.0 AHB Protocol-Based Designs
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Oct 24, 2006Link Will Help Accelerate Yield Ramp of High-Volume Production ICs
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Oct 23, 2006Comprehensive Test Flow Links Galaxy Platform With STAR Memory System
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Oct 19, 2006Tight Correlation Between Synthesis and Layout Reduces Time-to-Market
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Oct 17, 2006Significant Improvement in the Quality of At-Speed Testing Expected from Test Pattern Generation Based on Precise Timing
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Oct 17, 2006Expanded Collaboration Will Extend Saber Product Line Integration with UGS' NX MCAD and Teamcenter PLM Technology
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Oct 16, 2006Innovative Process-Aware DFM Product Family Enables Designers to Reduce Process Variability Impact and Improve Design for Advanced Semiconductor Manufacturing
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Oct 11, 2006Automated Power Network Prototyping Delivers Optimized Area and Layer Trade-offs
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Oct 9, 2006University to Receive World-Class Laboratory to Advance Education in Microelectronics Design
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Oct 9, 2006Synopsys JupiterXT and IC Compiler Tools Enable Die Size Optimization
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Oct 4, 2006Next-Generation Signal Integrity Sign-off Models to Deliver Improved Accuracy and Reduced Turnaround Time
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Oct 3, 2006SystemVerilog and the VMM Methodology Provide a Robust, Scalable Verification Environment
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Oct 2, 2006Predictable Performance and Excellent Support Essential for Development of High-Performance Microdisplays
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Sep 28, 2006Synopsys Recognizes Engineers' Technical Excellence With Best Paper Awards at SNUG Boston ConferenceMore Than 400 Engineers Gather at Eighth Annual Regional User's Conference
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Sep 27, 2006Second Consecutive Runtime Improvement for TetraMAX Tool Offers Designers Substantial Productivity Benefits
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Sep 25, 2006High-Performance Sitka Evaluation and Development Platform Allows Designers to Test and Debug Applications Using the DesignWare PCI Express IP in Hardware
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Sep 20, 2006Solutions Target Improved Lithography Modeling Accuracy, Reduced Time-to-Silicon, and Improved Manufacturing Yield
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Sep 19, 2006Technology Proven to Help Customers Achieve Ultra Low Power IC Designs
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Sep 19, 2006PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products
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Sep 15, 2006Synopsys Dedicates Scan Chain Inventions to Public Domain
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Sep 13, 2006Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups
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Sep 5, 2006High-Performance DesignWare IP for USB, PCIe, SATA and XAUI Now Available
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Aug 28, 2006Concurrent Multi-Mode Optimization Speeds Timing Closure
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Aug 21, 2006Topographical Technology Improves Designer Efficiency and Reduces Turnaround Time
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Aug 16, 2006Acquisition Will Enable Tighter Integration With DFM and Manufacturing Tools to Optimize Yield and Increase Predictability
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Aug 2, 2006Variation-based Models Built on Proven Composite Current Source Technology to Deliver Improved Accuracy
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Jul 27, 2006VhdlCohen Publishes A Pragmatic Approach to VMM Adoption: 'A SystemVerilog Framework for Testbenches'
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Jul 26, 2006EDA Company Honored for Key Contributions to Open Source Parser for Liberty™ Library Format
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Jul 26, 2006Checkers Proven to Accelerate Customer Adoption of SystemVerilog Assertions to Benefit Entire Industry
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Jul 25, 2006Scalable DFM Checks Accelerate Time-to-Yield for Designers
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Jul 24, 2006Toshiba to Deploy Integrated, Production-Proven DFM Technology into Standard Layout Flow
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Jul 24, 2006Built on Gold Standards, PrimeTime VX and Star-RCXT VX Tools Deliver Foundation for Comprehensive Variation-aware Design Solution for Sub-65nm Design
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Jul 24, 2006Integration of Production-Proven Design and Manufacturing Technology Accelerates Time to Yield
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Jul 20, 2006More Than 50 Tapeouts Prove DFT MAX Reduces Test Time and Cost
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Jul 19, 2006Multiple Multi-Voltage Tapeouts Completed With Galaxy Advanced Low-Power Solution
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Jul 19, 2006Common Platform Technology Reference Flow Adds Critical Area Design-for-Manufacturing Capability in IC Compiler
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Jul 18, 2006Reference Flow 7.0 Incorporates Latest Technologies for Low Power and Yield Optimization to Address 65-nanometer Design Challenges
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Jul 18, 2006Users Embrace the VMM Methodology for SystemVerilog and Synopsys' VCS® Native Testbench
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Jul 13, 2006Founding Technical Advisory Board Members to Hold Inaugural Meeting at Design Automation Conference in San Francisco
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Jul 12, 2006Synopsys Expands DesignWare Library With More Than 20 New IP Components
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Jul 11, 2006Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes
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Jul 5, 2006VCS Native Testbench (NTB) and the Verification Methodology Manual (VMM) for SystemVerilog Help Accelerate Aggressive Verification Schedule
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Jun 29, 2006Sunplus Selects Synopsys Professional Services to Achieve Aggressive Schedule and Cost Goals
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Jun 28, 2006Silicon-Proven DesignWare PHY Cuts Power and Size in Half for Portable, High-Volume Consumer SoCs
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Jun 28, 2006NanoTime Extends Synopsys' Leadership in Transistor-Level Simulation and Analysis
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Jun 27, 2006IC Compiler Reduces Chip Cost by Achieving Over 90% Area Utilization
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Jun 26, 2006Release Brings New Advances in Yield, Low Power, and Testability
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Jun 13, 2006Sentaurus TCAD Accelerates Advanced Technology Development With New Process and Device Modeling Capabilities
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Jun 13, 2006Synopsys' Galaxy™ Design and Discovery™ Verification Platforms and DesignWare® IP to Accelerate SoC Development
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Jun 7, 2006Bridge Delivers High-Throughput Connection to Multiple PCI Express Technology-Based Systems and Peripherals
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Jun 1, 2006
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May 25, 2006Automated Prototyping Flow Delivers Predictable Time-to-Tapeout
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May 17, 2006Industry's First Extraction Tool Verified for TSMC 65nm Designs
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May 17, 2006Complete Tool Suite From TCAD to Design to Mask Synthesis Enables Yield Enhancement Concurrently With Area, Timing and Power Optimization
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May 17, 2006DesignWare® Users Get Easy Access to TSMC's 65-nm Standard Cells, I/Os and Memory Compilers
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May 16, 2006Acquisition to Address Exponentially Growing Software Design Bottleneck
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May 15, 2006Enhanced Methodology Accelerates Time-to-Market for ARM Processors, Including Next-generation ARM Cortex-R4 Processor
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May 11, 2006Liberty Technical Advisory Board to Build on Composite Current Source Modeling Technology to Address Future Industry Needs
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May 8, 2006Accurate Prediction of Post-Layout Design Results in Synthesis Enhances Productivity and Accelerates Timing Closure
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May 3, 2006Sun Microsystems Executive to Present Keynote
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May 2, 2006Industry-Standard SystemVerilog Enables Advanced Verification of Complex VHDL Designs
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May 2, 2006Silicon-Proven Mixed-Signal PHYs Reduce Risk and Speed Time to Production for BiTMICRO's Flash Solid State Disk Drives
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Apr 26, 2006Interoperability With Hitachi Microdrive 3K8 CE-ATA Hard Drive Enables Rapid Adoption of CE-ATA Interface
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Apr 25, 2006VDA / FAT-AK30 Expands Reference Simulator Support of Mechatronic Libraries
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Apr 24, 2006Cites Predictability, Faster Time-to Market and Ease of Deployment as Key Benefits
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Apr 19, 2006New Book by Janick Bergeron Provides Techniques for Writing, Running, Debugging and Verifying the Correctness of SystemVerilog Testbenches
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Apr 19, 2006Agere Chooses Synopsys in Major Productivity Drive
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Apr 18, 2006DFT MAX Adaptive Scan Technology Enables Predictability Through First-Silicon Success
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Apr 17, 2006Synopsys' PSM Technology Enables Higher Yield for High-Performance Products
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Apr 3, 2006Galaxy's Complete RTL-to-GDSII Low-Power Solution Critical for Market Success
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Mar 30, 2006Synopsys Tools Aid Microelectronic Design in New Birck Nanotechnology Center
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Mar 28, 2006Aart de Geus and Steve Wozniak Address Nearly 1,300 Engineers at 16th Annual User's Conference
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Mar 28, 2006Synopsys Discovery™ Verification Platform Provides a Complete Verification Solution From System Level Through RTL to Gates
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Mar 28, 2006Institute to Receive World-Class Tools for Advancing Education in Electronic Design
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