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Highlights: New parallel synthesis execution capability delivers up to 3X faster runtime with smaller area and higher performance Physically-aware advanced synthesis provides up to 10 percent...

Highlights: Memory-efficient, multithreaded engines utilize available server cores to speed up automatic test pattern generation (ATPG) and silicon diagnosis Twenty-five percent fewer test...

Highlights: TetraMAX ATPG, DesignWare STAR Hierarchical System and STAR Memory System can be used with confidence to develop functionally safe automotive systems Tool and IP certification...

Highlights: Fuji Xerox reduced silicon area by more than 50 percent using an application-specific instruction set processor (ASIP) developed with ASIP Designer, compared to fixed hardware ASIP...

Highlights: DesignWare Cryptography IP solutions are compliant with SHA-3, the latest standard released by the National Institute of Standards and Technology IP solutions target a range of...

Highlights: TSMC selects Synopsys as its "Partner of the Year" for interface IP and tool enablement for the 5th consecutive year Synopsys' Digital and Custom Implementation tools and reference...

Highlights: Broad IP portfolio for IoT designs includes logic libraries, memory compilers, non-volatile memory, data converters, wired and wireless interface IP, security IP, processor cores and a...

Highlights: Synopsys' successful tape-out of IP for TSMC 10-nm process includes USB 3.1, USB 3.0, USB 2.0, HSIC, PCI Express 3.0, PCI Express 2.0 and MIPI D-PHY Tape-out of DesignWare IP enables...

Highlights: IC Compiler II certified for TSMC's 10-nm FinFET V0.9 process Certification includes a new reference flow for the full suite of digital, signoff and custom implementation tools from...

Synopsys, Inc. (Nasdaq:SNPS) today announced that TSMC has certified its IC Compiler™ II place and route product for V0.9 of 10-nanometer (nm) FinFET process technology (N10FF), and are on track...