Synopsys Announces Immediate Availability of Reprogrammable Non-Volatile Memory IP in 180-nm CMOS Process Technology
DesignWare AEON Embedded Non-Volatile Memory IP Improves Electrical Performance and Lowers Integration Risk for Wireless and Analog SoC Designs

MOUNTAIN VIEW, Calif., June 27, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate availability of DesignWare® AEON® Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP products include few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. Synopsys offers DesignWare AEON NVM IP for leading process technologies in more than 100 different memory configurations, all qualified to the appropriate industrial specifications. Implemented in standard CMOS process technology with no additional mask or process steps required, the DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs.

Synopsys' broad portfolio of MTP and FTP NVM IP solutions delivers optimized electrical performance for a wide range of end applications, including: performance trim and calibration in precision analog designs, data storage in ultra-low power wireless applications, or high endurance in real-time datalogging applications. These solutions help designers reduce the cost and risk of integrating NVM IP into their SoC designs.

A key advantage of the DesignWare AEON embedded NVM IP is that no high voltage generation circuitry is required – all programming and re-programming is done using a standard CMOS technology with no additional masks or process adaption. This allows designs to operate from a single core supply, eliminating the complication of generating a separate, high-voltage signal for NVM programming, or supporting a high-voltage I/O pad. In addition, DesignWare AEON NVM IP provides support for extended temperature ranges beyond industry standard (up to 125 degrees C for commercial and industrial products and up to 150 degrees C for automotive products), which enables designers to develop robust SoCs that can withstand harsh process, voltage and temperature variations. The DesignWare AEON products allow designers to choose the best configuration to optimize power, performance and area for their applications' SoCs:

  • AEON/FTP Trim: ideal for analog and mixed-signal SoC designs, this solution provides area efficiency (256 bits in < 0.07 mm2) and offers up to 100 write cycles and additional flexibility over one-time programmable (OTP) solutions
  • AEON/MTP RFID: targeting RFID and wireless SoC designs, this ultra-low power solution offers up to 1,000 write cycles, with read operation down to 1.0 V
  • AEON/MTP EEPROM: fully qualified to automotive grade standards (AEC-Q100), this product provides support for up to one million write cycles at high temperatures (up to 150 degrees C)


"Verayo's patented silicon 'DNA' technology – Physical Unclonable Functions (PUF) technology – provides an unclonable physical layer of security for our cost-effective RFID IC authentication solutions that target a broad range of mobile and near-field communication applications. For these RFID ICs, it is important for Verayo to leverage silicon-proven third-party IP that enable us to meet our strict cost and feature requirements," said Eric Duprat, CEO at Verayo. "Implementing Synopsys' DesignWare AEON NVM IP in our latest mixed-signal RFID IC provided our solution with value-add features such as customer programmability and improved the performance and area of the design, while reducing integration risk and helping us achieve our time-to-market window."


"Wireless and RFID companies are targeting the 180-nm process as the low-cost, high-performance node to deliver differentiated features and functionality in next-generation consumer electronics and automotive chip designs," said John Koeter, vice president of marketing for IP and Systems at Synopsys. "With reprogrammable NVM IP technology that has shipped in more than three billion chips and is now fully qualified for 180-nm process nodes, Synopsys offers SoC designers a proven solution optimized for power, area and performance that lowers their integration risk and speeds their time-to-market."


The DesignWare AEON embedded NVM IP for 180-nm process technology is available now for several leading foundries. DesignWare AEON embedded NVM IP is also available for leading 65-nm to 250-nm process technologies. For more information, visit:

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and Verification IP for widely used protocols, analog IP, embedded memories, logic libraries and configurable processor cores. In addition, Synopsys offers SystemC™ transaction-level models to build virtual prototypes for rapid, pre-silicon development of software. With a robust IP development methodology, reuse tools, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: Follow us on Twitter at

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at

Synopsys, AEON and DesignWare are registered trademarks or trademarks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

Editorial Contacts:

Sheryl Gulizia
Synopsys, Inc.

Stephen Brennan
650-968-8900 x11

SOURCE Synopsys, Inc.