MIPS Technologies and Synopsys Announce Galaxy™ Design Platform Reference Flow for High Performance 24K™ Core Family
Optimized Reference Flow Enables Customers to Hit Performance Targets Quickly

MIPS Technologies, Inc. (NASDAQ: MIPS) and Synopsys, Inc. (NASDAQ: SNPS) today announced the availability of a Galaxy™ Design Platform reference flow for MIPS Technologies' new high-performance 24K™ microprocessor core family. The 24K family (see related announcement from MIPS Technologies) is the highest performing synthesizable 32-bit microprocessor family available within the embedded industry, with up to 550 MHz performance, optimized design flows developed with leading EDA vendors, system-level on-chip interconnects and broad support from third party companies. The 24K core family was designed using products from Synopsys' industry-standard Galaxy platform, including Design Compiler®, DFT Compiler™, Physical Compiler®, Astro™, PrimeTime® and Star-RCXT™. The reference methodology includes flow documentation, floorplanning information, tool scripts and makefiles developed by MIPS Technologies, and enables users of the 24K family to replicate with high confidence the performance results that MIPS Technologies obtained using the Galaxy platform.

"MIPS Technologies is working with leaders such as Synopsys to ensure our customers have an optimized flow that will enable rapid implementation with a high degree of confidence using industry standard technology," said Victor Peng, vice president of engineering at MIPS Technologies. "The Galaxy platform exceeded our expectations during the development process and we expect customers using it will get their 24K core-based designs to market more quickly with reduced overall design requirements."

"Our focus with the Galaxy Design Platform is to produce the highest performing designs with the fastest time-to-results by reducing iterations with our convergent design flow," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "By working with MIPS Technologies to provide a reference flow for the 24K family, we can better support our joint customers by improving the convergence in their design process and increasing their confidence level in hitting their performance requirements."

Availability of the Reference Methodology

MIPS Technologies is offering customers of the 24K core family the Synopsys Galaxy Design Platform reference methodology with the relevant synthesis scripts and floorplanning information. Support for the reference methodology is provided by MIPS Technologies. For more details, visit the MIPS Technologies Website or contact the company at 650-567-5000 or email at sales@mips.com.

About the MIPS32 24K Family

The MIPS32 24K core family, which includes the 24Kc™, 24Kc Pro, 24Kf™ and 24Kf Pro versions, offers performance from 400 to 550 MHz worst case in a 0.13 micron process, the highest frequency available in 32-bit synthesizable cores for embedded markets, while minimizing design time and reducing product costs. Tailored SOC design methodologies, an Open Core Protocol (OCP) interconnect structure, standard libraries and on-chip memories from industry-leading companies help speed time-to-market, an important advantage for a processor core suited to embedded consumer applications such as digital and interactive TVs, set-top boxes and DVD players. For more information, visit the MIPS Technologies Website or contact the company at 650-567-5000 or email at sales@mips.com.

About MIPS Technologies

MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at 650-567-5000 or www.mips.com.

About Synopsys

Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .

NOTE: Synopsys, the Synopsys logo, Design Compiler, Physical Compiler, and PrimeTime are registered trademarks of Synopsys, Inc., and Astro, DFT Compiler, Galaxy, and Star-RCXT are trademarks of Synopsys, Inc. MIPS and MIPS32 are registered trademarks in the US and other countries, and MIPS-Based and 24K, 24Kc and 24Kf are trademarks of MIPS Technologies, Inc. All other products mentioned in this release are the intellectual property of their respective owners.

SOURCE: Synopsys, Inc.

CONTACT: Robert Smith of Synopsys, Inc., +1-650-584-1261, or
rsmith@synopsys.com; or Sarah Seifert of Edelman, +1-650-968-4033, or
sarah.seifert@edelman.com, for Synopsys; or Lee Garvin Flanagin of MIPS
Technologies, Inc., +1-650-567-5180, or flanigan@mips.com

Web site: http://www.mips.com/

Web site: http://www.synopsys.com/