Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that it has expanded its DesignWare® Mixed-Signal Intellectual Property (MSIP) portfolio with interface cell libraries to include application-specific memory I/Os optimized to support DDR/DDR2 and Mobile DDR SDRAM. In addition, Synopsys has added a suite of standards-based general purpose I/O libraries, which can be assembled with the complementary application-specific I/O libraries to develop robust system-on-chip (SoC) interface solutions. The DesignWare Mixed-Signal I/O Libraries are designed with an emphasis on signal integrity and ease of integration, enabling designers to more quickly achieve reliable, repeatable interface performance across a broad range of applications, such as feature-rich mobile handsets, digital still cameras, and mobile media players.

"We depend on Synopsys for proven, high-quality IP that will fit into a wide range of applications and still adhere to the signaling and quality standards required by our customers," said Rajesh Shah, Director of Engineering & IP at Open-Silicon, a fabless ASIC company. "We have been very successful implementing the DesignWare Mixed Signal I/O memory solutions in many of our customer's chips and look forward to continuing the relationship with Synopsys in this area to address the increasingly aggressive time to-market requirements."

The complexity and computational power of mainstream consumer electronics, computing and communication semiconductor devices have increased the challenges of implementing and integrating third-party semiconductor IP. Traditional piecemeal interface components are not sufficient to address the numerous signal integrity issues at higher operating frequencies. The DesignWare Mixed-Signal I/O Libraries combine proven interface design techniques, rigorous system interconnect validation, and documented integration and system engineering support in a suite of standards-based I/O libraries to meet today's interface IP requirements.

"Synopsys continues to expand its connectivity IP portfolio, this time with the introduction of the DesignWare Mixed-Signal I/O Libraries. These memory and general purpose I/Os enable designers to develop a broad range of high-performance, reliable system interfaces for mobile, communication and computing devices," said Guri Stark, vice president of Marketing, Solutions Group, Synopsys, Inc. "Synopsys delivers proven connectivity IP solutions that help our customers minimize SoC design risk and improve time-to-market, while allowing SoC designers to focus their efforts on designing differentiating features for their SoCs."

Availability

The DesignWare Mixed-Signal I/O Libraries, featuring the DDR2 SDRAM I/O Library, are available today for the TSMC 130-nanometer G process technology.

About DesignWare Mixed-Signal IP (MSIP)

Synopsys' comprehensive portfolio of high-performance mixed-signal PHY IP for the PCI Express®, SATA, XAUI and USB protocols, as well as a suite of I/O libraries, enables designers to quickly integrate high-performance interfaces into their next-generation SoCs. Available for industry-leading processes, the DesignWare MSIP portfolio meets the needs of today's high-performance SoC designs for the networking, storage, computing, and consumer electronics markets. The DesignWare MSIP offering is complemented by a comprehensive suite of digital controllers and verification IP to provide chip developers with a complete solution for SoC integration. Each MSIP can be licensed individually, on a fee-per-project basis, or users can opt for the Volume Purchase Agreement, which enables them to license all the MSIP in one simple agreement. For more information on DesignWare MSIP, visit: www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.

NOTE: Synopsys and DesignWare are registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

  CONTACT:
   Renae Veiga
   Synopsys, Inc.
   650-584-1902
   renae@synopsys.com

   Khyati Shah
   Edelman
   650-429-2769
   khyati.shah@edelman.com

SOURCE: Synopsys, Inc.

CONTACT: Renae Veiga of Synopsys, Inc., +1-650-584-1902, or
renae@synopsys.com; or Khyati Shah of Edelman, +1-650-429-2769, or
khyati.shah@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/designware

Web site: http://www.synopsys.com/