Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, today announced the availability of its DesignWare® PCI Express™ Physical (PHY) layer intellectual property (IP), which rounds out a complete PCI Express Endpoint IP solution. Based on Synopsys' silicon-proven 6.25 Gbps backplane and high-speed SERDES (serializer-deserializer) technology, the DesignWare PCI Express PHY is optimized to be half the size, with twice the sensitivity and twice the jitter margin as competing solutions. These characteristics enable higher yield, better interoperability, lower field returns and ease-of-use in end applications. By combining the new PHY with its industry-leading PCI Express digital controller core and verification IP, Synopsys is offering designers a low-risk, integrated digital and mixed-signal IP solution for PCI Express applications.

As high-volume products are beginning to require PCI Express functionality, designers are looking to embed both the digital core and mixed-signal PHY in their SoCs to reduce cost. Examples of PCI Express applications include high-speed graphics, video-enabled peripherals, along with other hardware connecting to PCs using Intel's recently released Grantsdale chip set.

"With the introduction of our PCI Express PHY, designers can lower risk and shorten their design time by acquiring the complete PCI Express mixed-signal, digital and verification IP solution from a single supplier," said Guri Stark, vice president of Marketing, Synopsys' Solutions Group. "A very small die size, along with performance margin will enable both first-time and experienced high-speed SERDES designers to more cost effectively achieve high-volume production."

Pricing and Availability

The DesignWare PCI Express PHY is available now for early adopters. Contact Synopsys for pricing information. Also available now are the DesignWare PCI Express Verification IP and Endpoint Controller core. Synopsys Professional Services offers high speed signaling expertise to help system and chip designers with their packaging and board designs.

About DesignWare IP

Synopsys' industry leading, high-quality DesignWare IP enables designers to create and verify innovative, cost-effective SoCs, ASICs and FPGAs. The broad portfolio includes industry leading connectivity IP Cores and Verification IP (e.g., USB 1.1, USB 2.0, USB 2.0 PHY, USB 2.0 On-The-Go, PCI, PCI-X, PCI Express, Ethernet, I2C), AMBA™ on-chip bus (logic, peripherals, verification IP) complete memory solution (e.g., memory controllers, BIST and models), high-speed datapath components, microcontrollers (8051, 6811) and Star IP processors and DSP core (e.g., IBM PowerPC® 440, Infineon C166™S and TriCore™1, MIPS32™ 4KE™, NEC V850E™, Philips CoolFlux™ DSP). When combined with our robust IP development methodology, extensive investment in quality and comprehensive worldwide technical support, DesignWare IP gives designers a fast, predictable and low-risk path to chip success. For a complete directory of Synopsys IP visit: www.synopsys.com/ipdirectory

For more information on DesignWare IP, visit: www.designware.com or call 1-877-4BEST-IP.

About Synopsys

Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

NOTE: Synopsys and DesignWare are registered trademarks of Synopsys, Inc. PCI Express is a trademark of PCI-SIG. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

SOURCE: Synopsys, Inc.

CONTACT: Troy Wood of Synopsys, Inc., +1-650-584-5717, or
twood@synopsys.com; or Andrea Zils of Edelman, +1-650-429-2731, or
andrea.zils@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/