Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, and UMC (NYSE: UMC)(TSE: 2303), today announced the availability of a 90-nanometer (nm) reference design flow that is optimized for low-power system-on-chip (SoC) designs. The validated RTL-to-GDSII design flow is based on Synopsys' Galaxy™ Design Platform, ARM® Artisan® SAGE-X™ standard cell library, and UMC's 90-nm process. It addresses leakage power challenges at 90-nm and provides advanced design-for-manufacturing (DFM) capabilities for faster yield ramp and lower development costs.

"At UMC, we recognize the importance of working with leading EDA companies such as Synopsys to deliver silicon-validated reference design flows that address the SoC design challenges encountered at nanometer technologies," said Ken Liou, director of the IP and Design Support Division at UMC. "This latest development with Synopsys is specifically designed to give customers the benefit of both companies' expertise to help them achieve first pass silicon success with reduced time and risk."

The reference design flow incorporates many of Synopsys' Galaxy Design Platform's low power and design-for-manufacturing innovations, including Power Network Synthesis (PNS) and Power Network Analysis (PNA) products, which are used to design power plans at the floorplanning stage. Other floorplanning capabilities include virtual flat floorplanning with physical hierarchy-aware global routing, virtual timing optimization, and macro placement with automatic hierarchy detection. Designers can create an optimized initial design floor plan using these advanced features to guide them to the next design steps in physical synthesis and place and route. By following this plan, designers can achieve faster timing closure and avoid design iterations. The reference design flow also features multi-threshold (MVth) optimization to take advantage of the available UMC 90-nm multi-threshold libraries for leakage power reduction. In addition, the flow supports advanced signal integrity capabilities to perform analyses for electro migration (EM) and voltage drop (IR) that are crucial in avoiding design failure in 90-nm and below designs.

"Our close relationship with UMC helps ensure that the reference flow will satisfy the demands of even the most advanced designers dealing with 90-nanometer process design issues in power optimization and design for manufacturing and yield," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "This collaboration builds upon UMC's advanced technology and Synopsys' Professional Services proven expertise to give designers access to an optimized path to silicon that delivers higher quality of results while speeding time to results."

Synopsys has brought several new DFM capabilities to the new 90-nm reference design flow. One example is the addition of timing-driven dummy metal insertion to specifically meet UMC's metal density requirements while maintaining timing closure, and automatic redundant via and via farm insertion. These new DFM capabilities can help designers improve reliability and are supported in Synopsys' place-and-route solution.

Availability

The UMC/Synopsys reference design flow is available now and can be accessed from UMC's website at http://www.umc.com/ .

About UMC

UMC is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including 90nm copper, 0.13um copper, and mixed signal/RFCMOS. UMC is also a leader in 300mm manufacturing; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. UMC employs approximately 10,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com/ .

About Synopsys

Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http:/www.synopsys.com .

NOTE: Synopsys is a registered trademark of Synopsys, Inc. Galaxy is a trademark of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

   Editorial Contacts:
   Pierre Golde
   Synopsys, Inc.
   650-584-4194
   golde@synopsys.com

   Khyati Shah
   Edelman Public Relations
   650-968-4033
   khyati.shah@edelman.com

SOURCE: Synopsys, Inc.

CONTACT: Pierre Golde of Synopsys, Inc., +1-650-584-4194, or
golde@synopsys.com; or Khyati Shah of Edelman Public Relations,
+1-650-968-4033, or khyati.shah@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/