Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Sunplus Technology Co. Ltd. (TSE: 2401), a leading supplier of consumer ICs, has taped out a large high-density consumer design with Synopsys' IC Compiler next-generation physical implementation solution. Sunplus chose Synopsys design consultants and the IC Compiler tool to complete the entire physical layout of this design within 30 days to meet Sunplus' market opportunity. The challenge faced by the design team was to achieve the chip's performance target while not exceeding the tight die-size constraint. By achieving a utilization of close to 90 percent, IC Compiler minimized the die size and significantly lowered the chip cost.

"For this kind of consumer design, unit cost and time-to-market are absolutely critical," said George Chou, director in the Design Methodology Service Division of Sunplus. "The combination of Synopsys' next-generation physical implementation technology and expert design services allowed us to maximize productivity while meeting both our performance and time-to-results goals."

Synopsys' IC Compiler solution and sub-flows from the Pilot Design Environment were used to achieve Sunplus' aggressive performance and schedule goals for this 2.5-million-gate design. IC Compiler users have consistently reported 2X faster turnaround time, on average. Much of this productivity boost can be attributed to the Extended Physical Synthesis (XPS) technology that unifies optimizations across synthesis, placement, clock tree, and routing. In the case of the Sunplus project, this cost-sensitive consumer design also demanded that the die size be as small as possible. As a result, the layout was compressed to a very high 88% utilization. Despite the high density, IC Compiler was able to close timing across both functional modes -- mission mode and test mode -- and achieve the target frequency.

"The benefits of using the IC Compiler technology were clearly evident during this joint effort between Synopsys and Sunplus," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "The speed with which Sunplus was able to deliver results clearly exemplifies how Synopsys' combination of tools and expertise enhances the productivity of our partners in immediate and measurable ways."

About IC Compiler

The IC Compiler tool is Synopsys' next-generation place-and-route solution. It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Current-generation solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations. IC Compiler's Extended Physical Synthesis (XPS) technology breaks down the walls between these steps by extending physical synthesis to full place-and-route. IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies. It is a complete place-and-route system with everything necessary to do next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoC's). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.

NOTE: Synopsys is a registered trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

  Editorial Contacts:
  Sheryl Gulizia
  Synopsys, Inc.
  650-584-8635
  sgulizia@synopsys.com

  Tara Yingst
  Edelman
  650-429-2731
  tara.yingst@edelman.com

SOURCE: Synopsys, Inc.

CONTACT: Sheryl Gulizia of Synopsys, Inc., +1-650-584-8635, or
sgulizia@synopsys.com; or Tara Yingst or Edelman, +1-650-429-2731, or
tara.yingst@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/