Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, today announced that Toshiba Corporation, a world-class supplier of semiconductors, has taped out multiple 90-nanometer (nm) system-on-chip (SoC) designs for its audiovisual and office equipment product lines using Synopsys' Galaxy™ Design Platform. The designs were created using Design Compiler® and DesignWare® Library for synthesis, Power Compiler™ for dynamic and leakage power optimization, Physical Compiler® and Astro™ for physical implementation, PrimeTime® for delay calculation/static timing signoff, Star-RCXT™ for full-chip parasitic extraction signoff, and DFT Compiler™ SoCBIST for test. On its most recent design using the latest release of Astro, Toshiba was able to significantly boost design productivity, enabling a fast design turnaround time.

"Synopsys' Astro is an integral part of our design methodology and we use it for complex SoCs over five million gates," said Takashi Yoshimori, technology executive, Toshiba Corporation Semiconductor Company. "The correlation between Astro, PrimeTime and Star-RCXT has resulted in improved timing convergence, and has improved the predictability of our design schedule. Astro has helped us boost our design productivity in the entire physical implementation process. As a result, we have adopted it as the standard physical optimization tool in our flow. Since Astro supports both flat and hierarchical design, Toshiba is able to effectively utilize over 50 million gates capacity using our 90-nanometer process technology."

"The productivity gain realized by using Synopsys' Galaxy platform in our advanced design flow enables our designers to turn around designs very quickly," stated Masataka Matsui, senior manager of the Digital Media SoC Department, SoC Research & Development Center, Toshiba Corporation Semiconductor Company. "Using Synopsys' tools, we have already taped out complex high-performance digital media processors for multimedia applications with very high clock speeds. Astro will be used as the standard tool to develop our MeP high-end media embedded processor implemented in our 90-nanometer and below process technology."

"Synopsys' Astro technology is critical to the success of our designs," said Yoshiki Hayakashi, senior manager of the Digital Consumer SoC Group, Custom SoC Technical Marketing & Engineering Department, Toshiba Corporation Semiconductor Company. "Astro's streamlined, easy-to-use and highly productive environment allows our designers to quickly turn around their designs, and with the other Synopsys tools in our design flow, we are able to reuse existing design data."

"Customers such as Toshiba are increasingly turning to design productivity solutions like Astro in order to get their products to market quickly," said Antun Domic, senior vice president and general manager of the Implementation Group at Synopsys. "Toshiba has consistently increased its adoption of Galaxy technology in its advanced design flow. This has enabled Toshiba to deliver advanced, leading-edge chips to their customers."

About Synopsys

Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .

NOTE: Synopsys, Design Compiler, DesignWare, Physical Compiler and PrimeTime are registered trademarks of Synopsys, Inc., and Astro, DFT Compiler, Power Compiler, Galaxy and Star-RCXT are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

SOURCE: Synopsys, Inc.

CONTACT: Robert Smith of Synopsys, Inc., +1-650-584-1261, or
rsmith@synopsys.com; or Sarah Seifert of Edelman Public Relations,
+1-650-429-2776, or sarah.seifert@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/