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Oct 29, 2019

Synopsys Accelerates Cloud Computing SoC Designs with New Die-to-Die PHY IP in Advanced 7nm FinFET Process

DesignWare Die-to-Die PHY Enables Ultra- and Extra-Short Reach Connectivity in Large, Multi-Chip Module Designs

Highlights: Ultra-low power DesignWare Die-to-Die PHY IP delivers less than 1pJ/bit for optimal energy efficiency in hyperscale data centers Compact analog front-end enables reliable links up to...
Oct 29, 2019

Synopsys Ships More Than 3,000 HAPS-80 Prototyping Systems

HAPS-80's High Performance and Cost Effectiveness Has Driven Adoption by More Than 100 Companies

Synopsys, Inc. (Nasdaq: SNPS) today announced that it has shipped more than 3,000 HAPS®-80 prototyping systems since its introduction. HAPS-80 is deployed at more than 100 companies worldwide,...
Oct 28, 2019

NSITEXE Achieves First-Pass Silicon Success for High-Performance Data Flow Processor-based SoC Test Chip Using DesignWare IP

Silicon-Proven DesignWare Interface and Foundation IP Portfolios Lower Integration Risk and Accelerate Time to Market for Automotive Application

Highlights: DesignWare Controller and PHY IP for PCI Express and LPDDR accelerates development of the advanced data flow processor-based SoC Embedded Memories and Logic Libraries offer options for...
Oct 23, 2019

Astera Labs Accelerates PCI Express 5.0 System Deployment in Collaboration with Intel and Synopsys

Astera Labs Delivers Industry's First Commercially Available PCIe 5.0 Retimer SoC

MOUNTAIN VIEW, Calif., Oct 23, 2019 Highlights: Astera Labs' Aries Smart Retimer is the industry's first 32GT/s retimer SoC designed to the PCIe 5.0 specification. It doubles the signal reach and...
Oct 22, 2019

Synopsys Launches New ARC VPX DSP Processor IP for High-performance Signal Processing SoC Designs

DesignWare ARC VPX5 and VPX5FS DSP Processors Incorporate Ultra-wide Vector Architecture to Accelerate Highly Parallel Automotive, Sensor Fusion, and Communications Applications

Highlights: Synopsys ARC VPX5 and VPX5FS DSP Processors are based on an extended instruction set and VLIW/SIMD architecture optimized for highly parallel processing Multiple vector floating-point...

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