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Sep 23, 2013

Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design

Highlights: Multi-year collaboration delivers proven 16-nm design flow and methodology Synopsys tools are under V0.5 certification and moving...
Sep 19, 2013

Synopsys Announces Immediate Availability of Broad Portfolio of Interface IP for TSMC's 20SoC Process

Silicon-proven Synopsys IP Portfolio on TSMC's 20SoC Process Technology Enables Designers to Reduce Power Consumption and Increase Performance for Mobile and Multimedia SoC Designs

Highlights: Synopsys's DesignWare® IP portfolio for TSMC 20SoC includes USB, DDR, PCI Express®, and MIPI® PHY IP Silicon-proven IP...
Sep 12, 2013

Latest Release of Synopsys' CODE V Enables Faster, More Robust Optical Design Optimization

CODE V version 10.6 is now generally available

Highlights: Unique optimization algorithm speeds design of optical systems with superior image quality Customizable charts provide enhanced...
Sep 11, 2013

Synopsys Demonstrates Industry's First SuperSpeed USB Inter-chip (SSIC) Interoperability

Successful SSIC Interoperability Reduces Integration Risk and Speeds Time-to-Market for Mobile and Wireless Designs

Highlights: Synopsys demonstrates industry's first SSIC interoperability at Intel Developer Forum 2013, September 10-12 in San Francisco,...
Sep 9, 2013

Synopsys Announces DesignWare STAR Hierarchical System to Accelerate Silicon Testing of SoCs

Significantly Reduces Test Integration Time and Improves Test QoR for Hierarchical SoCs

Highlights: Increase design and design-for-test (DFT) productivity with automatic test integration and validation of system-on-chip (SoC),...

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