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Mar 12, 2015

Synopsys and Hardent Provide Interoperable Display IP Solutions to Reduce Data Transmission Bandwidth for Ultra High-Definition Mobile Devices

Combination of Synopsys DesignWare MIPI DSI IP and Hardent VESA Display Stream Compression IP Enables Single and Dual High-Definition Displays

Highlights: The compliant and interoperable DSI solution reduces data transmission bandwidth by compressing and transmitting video signals through existing display interfaces for ultra-high resolution
Mar 12, 2015

Synopsys' New Verification IP for MIPI SoundWire Enables Audio and Control Interfaces in Low Power Designs

Native SystemVerilog-based VIP for SoundWire Expands Portfolio of VIP for Mobile Applications and Offers Built-in Coverage, Verification Plan and Protocol-aware Debug

Synopsys, Inc. (NASDAQ: SNPS) announces the availability of verification IP (VIP) for the MIPI® Alliance SoundWireSM 1.0 specification. Synopsys VIP for MIPI SoundWire is based on a native...
Mar 10, 2015

Synopsys Galaxy Design Platform Enables 90 Percent of Volume-Production FinFET Designs

Vast Majority of Designers Choose Synopsys Implementation Tools for Move from Test Chips to Production Tapeout

Highlights: Galaxy Design Platform used for 90 percent of production FinFET designs Strong platform adoption underscores Synopsys' leadership in digital and custom design implementation tools for...
Mar 10, 2015

Synopsys Galaxy Design Platform Deployed by HiSilicon Technologies for Implementation of FinFET Designs

Successful Tapeouts Include the Newly Announced 64-bit ARM Cortex-A72 Processor-based SoC

Highlights: Design Compiler Graphical and IC Compiler save several weeks of design time by minimizing iterations between synthesis and place and route IC Compiler achieves HiSilicon Technologies'...
Mar 9, 2015

Synopsys' IC Compiler II Enables Toshiba's Tapeout of Complex 40-nm SoC, Proves out Game-Changing Capabilities

Toshiba Standardizes on IC Compiler II for Physical Design

Highlights: IC Compiler II enables Toshiba's successful tapeout of advanced 40-nm SoC 6X faster design turnaround time with one-third of the memory footprint 60 percent smaller buffer area during...

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