MOUNTAIN VIEW, Calif., Oct 29, 2018 /PRNewswire/ --

Highlights:

• SpyGlass DFT ADV provides ISO 26262 Single Point Fault Metric (SPFM) calculation based on the effects of soft errors
• Fast static analysis at the RTL- or gate-level ensures minimum impact to design schedule
• Generation of ordered lists of design blocks and registers negatively impacting the SPFM enables automated and efficient design improvements
• Analysis-driven changes with IC Compiler II and verification with Formality ensures the most efficient and robust design changes

Synopsys, Inc. (Nasdaq: SNPS) today announced the general availability of new soft-error analysis functionality within its SpyGlass^® DFT ADV tool. Output of this analysis directly guides efficient design changes resulting in targeted ISO 26262 functional safety metric improvements at the lowest cost. Analysis can be performed early in the design flow on either RTL- or gate-level netlists, minimizing impact to design schedules. Analysis takes just hours on even the largest designs. SpyGlass DFT ADV is fully ISO 26262 certified, enabling use on automotive designs.

Transient faults caused by soft errors can cause catastrophic failures during the operation of safety-critical electronic devices. The probability of avoiding such failures is reflected in the SPFM defined by the ISO 26262 functional safety standard. Minimum required SPFM values are specified by the standard for each of the defined automotive safety levels. Since the main effect of a soft error is an unintended change in the state of a register, a common approach to increasing a design's SPFM value is to use error-tolerant registers, such as those using a triple-flop voting approach. Usage of such registers must be very selective to minimize area overhead.

"Addressing soft-error effects is a critical component towards achieving necessary functional safety levels for our designs," said Akio Hirata, chief engineer, Fundamental Technology Development Group, Technology and Product Development Center at Panasonic Industrial Devices Systems and Technology Co., Ltd. "The fast metric analysis and flop identification provided by SpyGlass DFT ADV allows us to achieve necessary ISO 26262 SPFM levels while meeting aggressive area overhead constraints and design turnaround time goals."

The SpyGlass DFT ADV tool calculates SPFM metrics early in the design cycle. A unique static analysis approach based on signal probability propagation accurately estimates the SPFM metric for any portion of a design. Using this approach provides design teams the ability to identify and efficiently address SPFM hotspots. At the lowest level, a list of the design's flip-flops is generated and ordered based on each flop's contribution to SPFM loss. The minimum number of regular flops needing to be replaced with error-tolerant ones to achieve the desired SPFM value can then easily be determined. Flop substitutions are then performed within the place-and-route flow based on the generated minimum list. When coupled with IC Compiler^™ II place-and-route through Synopsys' Test Fusion technology, further optimizations, such as ensuring minimum flop spacing within the added triple-flop registers to avoid multiple-upset events, can also be seamlessly achieved. All changes can then be verified with Formality^® equivalence checking to ensure design consistency. Alternatively, larger blocks of logic contributing an aggregate SPFM loss can be managed using other techniques, such as adding redundant blocks or through the addition of safety monitors. Once the design has been completed, final SPFM metric verification can then be performed using simulation-based fault injection techniques, such as those offered by Synopsys' Z01X^™ functional safety assurance solution.

"Our customers are increasingly concerned about meeting necessary functional safety levels in their designs," said Steve Pateras, senior director of marketing for Test Automation in Synopsys' Design Group. "We continue to focus on providing solutions that assist our customers in achieving necessary safety metrics with minimal impact to their designs and overall development schedules."

For more information on the comprehensive Synopsys Test solution, visit www.synopsys.com/test.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:

James Watts
Synopsys, Inc. 
650-584-1625
jwatts@synopsys.com

SOURCE Synopsys, Inc.