Synopsys Introduces USB 3.1 Type-C IP with DisplayPort 1.3 and HDCP 2.2 for High-Bandwidth Data Transfer with Content Protection
DesignWare IP Solution Accelerates Development of SoCs Delivering Secure Video, Data and Power over a Single USB Type-C Connector
MOUNTAIN VIEW, Calif., Jan. 26, 2016 /PRNewswire/ --
- Industry's most comprehensive USB Type-C IP solution includes USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers with HDCP 2.2 content protection, and verification IP
- HDCP 2.2 security protocol, incorporated in DesignWare USB-C 3.1/DisplayPort 1.3 controllers, protects audio/video content during transfer over the USB Type-C connector
- DisplayPort 1.3 in USB Type-C Alt Mode supports 8.1 Gbps per lane and up to 8K resolution for Ultra High-Definition TVs and monitors
- Support for the latest USB Type-C Port Controller specification enables flexible hardware and software partitioning to implement differentiating USB Type-C features while maintaining USB Type-C compatibility
- DesignWare USB-C 3.1/DisplayPort 1.3 IP subsystems, IP prototyping kits and IP software development kits, as part of the IP Accelerated initiative, reduce the time and effort of integrating the IP into SoCs
Synopsys, Inc. (Nasdaq: SNPS) today introduced the new DesignWare® USB-C 3.1/DisplayPort 1.3 IP solution which integrates USB Type-C™ (USB-C™), SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) and DisplayPort 1.3 interfaces with High-bandwidth Digital Content Protection (HDCP) 2.2 IP. The solution accelerates development of mobile and digital office system-on-chips (SoCs) that require 10 Gbps data transfer and delivery of secure audio/video content and power through a single USB Type-C connector. Synopsys is the first to provide a USB Type-C IP solution that incorporates the HDCP 2.2 protocol, which is increasingly required for DisplayPort Alt Mode implementations to protect premium content during transmission. Support for the new USB Type-C Port Controller specification provides flexible hardware and software partitioning options so designers can manage system costs and features. The DesignWare USB-C 3.1/DisplayPort 1.3 IP subsystems, IP prototyping kits, IP software development kits and verification IP enable designers to quickly incorporate and verify the latest high-performance USB Type-C interfaces in their SoCs.
The DesignWare USB-C 3.1/DisplayPort 1.3 IP solution delivers up to 10 Gbps data rates and supports USB Type-C, the newest USB cable and connector developed by USB-IF, to improve the user experience with reversible plug orientation and cable direction, bi-directional power and Alternate Modes. The DisplayPort Alt Mode uses existing SuperSpeed USB lanes over USB Type-C connectors and cables to deliver up to 32.4 Gbps maximum link bandwidth with each of the four lanes running at 8.1 Gbps. This 50 percent increase in bandwidth over DisplayPort 1.2 enables Ultra High-Definition (UHD) TVs and monitors with up to 8K resolution. The DesignWare USB-C 3.1/DisplayPort 1.3 IP solution simplifies integration and reduces system-level costs by removing requirements for external switch components for the USB and DisplayPort datapaths.
The DesignWare USB-C 3.1/DisplayPort 1.3 IP solution is the industry's first to integrate HDCP 2.2 content security, which is the latest evolution of content protection technology. HDCP 2.2 content security is required to play back UHD 4K and higher-resolution content over DisplayPort Alt Mode. It creates a secure connection between a source and display by using industry standard public key and advanced encryption algorithms for successful content transfer. Synopsys' HDCP 2.2 content protection IP provides designers with a complete and highly secure implementation of the HDCP 2.2 standard, including the entire control plane processing with authentication and key exchange protocols, as well as key stream generation. Incorporating HDCP 2.2 content protection in the DesignWare USB-C 3.1/DisplayPort 1.3 IP solution helps designers meet the stringent compliance requirements of the DCP LLC licensing authority.
The DesignWare USB-C 3.1/DisplayPort 1.3 IP solution is based on Synopsys' certified, silicon-proven SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) solution that has been successfully integrated into a wide range of customer SoCs. The solution meets the USB-IF standard specifications, including 10 Gbps performance and 5 V and 3.3 V tolerance, and is backward compatible with USB 3.0 and 2.0.
Image: DesignWare USB-C 3.1/DisplayPort 1.3 TX PHYs show open eyes at the maximum data rates of each specification.
"Synopsys has been an active member of USB-IF for more than 18 years, and their USB IP solutions are used to ease the integration and adoption of the latest USB interfaces," said Jeff Ravencraft, USB-IF President and COO. "Synopsys' introduction of new products that support the latest USB-IF specifications will help designers who are using USB-C to quickly incorporate this technology into their SoCs."
"With the increasing adoption of USB Type-C Alt Modes, designers are requiring functionality that enables the transfer of secure audio/video, data and power through a single USB Type-C connector," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "By providing a complete, integrated DesignWare USB-C 3.1/DisplayPort 1.3 IP solution with HDCP 2.2 content protection IP, Synopsys enables designers to accelerate the integration of high-performance USB Type-C connectivity into their SoCs, while enabling secure delivery of high-definition video content."
Availability & Resources
The DesignWare USB-C 3.1/DisplayPort 1.3 PHYs for FinFET process technologies and HDCP 2.2 content protection IP are available now. The DesignWare USB-C 3.1/DisplayPort 1.3 Controllers and IP Subsystems are scheduled to be available in Q3 2016. Please contact Synopsys for availability information on the related DesignWare IP Prototyping Kits and IP Virtualizer™ Development Kits.
About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
This press release contains forward-looking statements within the meaning of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected release and benefits of the DesignWare USB-C 3.1/DisplayPort Controllers and IP subsystems. Any statements that are not statements of historical fact may be deemed to be forward-looking statements. These statements involve known and unknown risks, uncertainties and other factors that could cause actual results, time frames or achievements to differ materially from those expressed or implied in the forward-looking statements. Other risks and uncertainties that may apply are set forth in the "Risk Factors" section of Synopsys' most recently filed Annual Report on Form 10-K. Synopsys undertakes no obligation to update publicly any forward-looking statements, or to update the reasons actual results could differ materially from those anticipated in these forward-looking statements, even if new information becomes available in the future.
SOURCE Synopsys, Inc.