MOUNTAIN VIEW, Calif. and CAMBRIDGE, England, Feb. 21, 2013 /PRNewswire/ --
Highlights:
ARM (LON: ARM; Nasdaq: ARMH) and Synopsys, Inc. (Nasdaq: SNPS) today announced a collaboration to optimize performance of ARM® Mali™ graphics processing units (GPUs) in 20-nanometer (nm) and smaller process geometries using the Synopsys Galaxy™ Implementation Platform. The companies successfully taped out the first ARM Mali-T658 design using a 20nm process technology, ARM Artisan® physical IP and shader functionality. The resulting RTL-through-sign-off design flow includes double-patterning support throughout. The ongoing collaboration will help designers optimize the implementation of Mali GPUs for their target applications.
"Mali GPUs are found in most Android™ tablets and smart digital TVs currently shipping, and are one of the most popular graphics solutions for smartphones. Users' demand for advanced graphics continues to increase, which means that optimizing GPUs for selected end devices is essential," said Pete Hutton, general manager, Media Processing Division, ARM. "Building on a long history of successful collaborations with Synopsys, this implementation will enable designers to optimally implement ARM Mali-T600 family GPUs using Synopsys tools in sub 20nm leading-edge process technologies."
The Mali-T600 series includes five members (Mali-T604, Mali-T624, Mali-T628, Mali-T658 and Mali-T678), which have all been designed to provide exceptional graphics performance and they feature the first graphics technology to bring GPU compute functionality into mobile devices. This combined functionality brings additional hardware complexity which is further compounded by the new double-patterning requirements introduced by 20nm and below technologies.
Smaller process technologies, such as 20nm and below, require a highly integrated design flow for fast closure while delivering optimal results. The collaboration used the Galaxy Implementation Platform to produce a methodology tuned for the Mali GPU with ARM Artisan physical IP in 20nm. Primary tools used included Synopsys' Design Compiler® synthesis, Formality® formal verification, DFTMAX™ and TetraMAX® test, IC Compiler™ layout, StarRC™ extraction and PrimeTime® timing analysis and signoff. In addition, IC Validator In-Design capabilities for physical verification were used during the implementation process to speed design closure. The methodology also benefitted from the use of DC Explorer & Dataflow Analyzer to perform early exploration, especially of floorplans and macro placement so critical to GPU performance.
"Twenty-nanometer and smaller process technologies introduce new complexity requiring early and deep technical collaboration among semiconductor ecosystem partners," said Antun Domic, senior vice president and general manager, Implementation Group, Synopsys. "Through this collaboration with ARM, the Synopsys Galaxy Implementation Platform with In-Design physical verification combines with the ARM Mali IP and Artisan physical IP to provide a proven, DPT-compliant solution that will help accelerate the time to design closure on complex SoCs at 20 nanometers and below."
About ARM
ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
ARM is a registered trademark of ARM Limited. Synopsys, Design Compiler, Formality, TetraMAX and PrimeTime are registered trademarks of Synopsys, Inc. registered in the United States and/or other countries. All other trademarks mentioned in this release are the intellectual property of their respective owners.
Safe Harbor Statement
This press release contains forward-looking statements within the meaning of Section 27A of the United States Securities Act of 1933 and Section 21E of the United States Securities Exchange Act of 1934, including statements regarding the expected outcome and benefits of the agreement and collaboration between Synopsys and ARM, including expected customer results with ARM and Synopsys solutions. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, technical or other difficulties in developing solutions, market acceptance of these solutions, unforeseen production or delivery delays, failure to perform as expected, product errors or defects and other risks as identified in the companies' respective filings with the U.S. Securities and Exchange Commission, including those described in the "Risk Factors" section of Synopsys' latest Annual Report on Form 10-K.
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Editorial Contacts: |
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Tiffany Sparks |
Sheryl Gulizia |
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ARM |
Synopsys, Inc. |
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+1 408 576 1397 |
650-584-8635 |
SOURCE Synopsys, Inc.
