Joint Collaboration Aims to Deliver Complete Design Flow for the 32-nm Process

Enhancements to Industry's Most Proven Verification Methodology Include New Base Classes and Performance Analyzer Application

High-Quality, Silicon-Proven DesignWare IP Lowers Design Risk and Enables Interoperability with Hi-Speed USB Products

Addition of Altera Stratix III FPGA-based prototyping boards targets algorithmic design and early software development

Advanced Routing And Lower Clock Skew Seen As Critical For High-Performance Designs

Asset Acquisition to Facilitate Expansion in the Fast-Growing Rapid Prototyping Segment

Modern Architecture and Unified Design and Verification Environment Key to Productivity

Companies Select Synopsys DesignWare IP as Preferred Solution for SoC Designs

Enhanced Composite Current Source (CCS) Modeling Technology Reduces Library Data Size by 75 Percent; Improves EDA Tool Efficiency by up to 60 Percent

DesignWare SuperSpeed USB IP Solution Eases Integration Effort for High Performance SoC Designs

Property and Parameter Definitions Contribution Will Help Enable Standardized PDKs and Custom IC Design Interoperability

Topics include 3rd party EDA tool integration with Galaxy Custom Designer™ solution and IPL Alliance Updates

Ease of Deployment Critical in Meeting Time-to-Market Requirements

Complete, Silicon-proven SATA IP Solution Consisting of Digital Controllers, PHY and Verification IP Lowers Risk and Speeds Time-to-market for SoC Designs

Unique Power-Aware Test Capabilities Reduce Yield Loss

Collaboration accelerates growth of rising industries in Japan

Tenth Annual Boston Event Draws Record Attendance of 434 Engineers and is Part of Largest User Conference Program in EDA

Productivity Achieved Deploying Galaxy Design Platform and Discovery Verification Platform Cited as the Key Decision Criteria

Faster Runtime, Enhanced Design Closure, and Increased Automation Boost Designer Productivity

Synopsys' Saber and System Studio products qualified on Windows HPC Server 2008