New Book Teaches Techniques to Develop an Effective SVA-Based Verification Strategy

Enhanced STARCAD-CEL Methodology Accelerates Time-to-Market for Major Japanese Semiconductor Companies

Synopsys Galaxy Design Platform and PrimeRail Deliver Complete Flow for Multi-threshold CMOS Design

Builds Electronic Design Automation Industry's First Supercomputer to Claim 242nd Spot on Top500 List

Simple Implementation and Predictable Results Were Key Drivers in Selection

Combination of Design and Verification Platforms With DesignWare® IP Meets Tight Area, Power and Performance Goals

Freescale Deploys VCS Native Testbench for SystemVerilog-Based Verification

IC Compiler Enables 10 Percent Die-Size Shrink and 2X Faster Turnaround Time

San Jose Mercury News High-Tech Journalist to Present Keynote

Complete Solution Will Include Memory Controller and Mixed-Signal PHY to Reduce Risk and Speed System Integration

Bridge Connects a Wealth of PCI Express Technology-Based Systems and Peripherals to AMBA 2.0 AHB Protocol-Based Designs

Link Will Help Accelerate Yield Ramp of High-Volume Production ICs

Comprehensive Test Flow Links Galaxy Platform With STAR Memory System

Tight Correlation Between Synthesis and Layout Reduces Time-to-Market

Significant Improvement in the Quality of At-Speed Testing Expected from Test Pattern Generation Based on Precise Timing

Expanded Collaboration Will Extend Saber Product Line Integration with UGS' NX MCAD and Teamcenter PLM Technology

Innovative Process-Aware DFM Product Family Enables Designers to Reduce Process Variability Impact and Improve Design for Advanced Semiconductor Manufacturing

Automated Power Network Prototyping Delivers Optimized Area and Layer Trade-offs

University to Receive World-Class Laboratory to Advance Education in Microelectronics Design

Synopsys JupiterXT and IC Compiler Tools Enable Die Size Optimization