AMCC Deploys SystemVerilog Verification Environment With Synopsys' VCS® Native Testbench and Reference Verification Methodology

PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products

Provides Complete Set of Standards-Based I/O Libraries for General Purpose and High-Performance Applications

DesignWare PHYs for Hi-Speed USB 2.0 and Hi-Speed USB OTG Developed with TSMC's Production-Proven 90-nm Libraries

Increased Predictability of Manufacturing Process through TCAD Lowers Product Development Cost and Time

IC Compiler Fits Easily in the Agere Flow, Delivers Higher Performance

Reference Design Flow Features Low Power Management and Design-for-Manufacturing Automation Capabilities

TetraMAX® ATPG Performance Speedup Combined with a New Waveform Debugger Streamline Test Pattern Generation for Complex Designs

Designers Benefit from Enhanced Productivity and Reduced Design Margins

Composite Current Source Model First to Combine Timing, Noise and Power

Combined Technology Can Read, Write and Provide On-The-Fly View of Compressed Files

DFT MAX Achieves 90% Test Data Volume Reduction for Flat Display TV Controller

Exar Develops and Deploys Advanced SystemVerilog Verification Environment and Reference Model with VCS® Native Testbench Technology

TetraMAX Diagnostics Enable TSMC to Accelerate Yield Ramp on Deep Submicron Designs

Advanced Testbench Techniques Critical for Multi-Protocol Verification Environment at Chip and System Levels

Project Methodology Leverages Assertions, Functional Coverage, Constrained-Random Stimulus Generation and PCI Express® Verification IP

Sentaurus Sets New Standard in TCAD Simulation Capabilities for Semiconductor Process, Device, Circuit and System Analysis, and Parametric Yield Optimization

Communications Leader Uses Synopsys' Tools and Flows From Design Through Physical Implementation