Next-Generation Signal Integrity Sign-off Models to Deliver Improved Accuracy and Reduced Turnaround Time

SystemVerilog and the VMM Methodology Provide a Robust, Scalable Verification Environment

Predictable Performance and Excellent Support Essential for Development of High-Performance Microdisplays

More Than 400 Engineers Gather at Eighth Annual Regional User's Conference

Second Consecutive Runtime Improvement for TetraMAX Tool Offers Designers Substantial Productivity Benefits

High-Performance Sitka Evaluation and Development Platform Allows Designers to Test and Debug Applications Using the DesignWare PCI Express IP in Hardware

Solutions Target Improved Lithography Modeling Accuracy, Reduced Time-to-Silicon, and Improved Manufacturing Yield

Technology Proven to Help Customers Achieve Ultra Low Power IC Designs

PSM Technology Enhances Lithography Resolution and Yield for High-Performance Products

Synopsys Dedicates Scan Chain Inventions to Public Domain

Provides 100 Percent of the OCP-IP Defined Functional Coverage Groups

High-Performance DesignWare IP for USB, PCIe, SATA and XAUI Now Available

Concurrent Multi-Mode Optimization Speeds Timing Closure

Topographical Technology Improves Designer Efficiency and Reduces Turnaround Time

Acquisition Will Enable Tighter Integration With DFM and Manufacturing Tools to Optimize Yield and Increase Predictability

Variation-based Models Built on Proven Composite Current Source Technology to Deliver Improved Accuracy

VhdlCohen Publishes A Pragmatic Approach to VMM Adoption: 'A SystemVerilog Framework for Testbenches'

Checkers Proven to Accelerate Customer Adoption of SystemVerilog Assertions to Benefit Entire Industry